[v5,0/4] fix the meson NFC clock

Message

Liang Yang May 13, 2022, 12:34 p.m. UTC

EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK'
which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is
the divider and bit6~7 is the mux for fix pll and xtal. At the beginning,
a common MMC and NAND sub-clock was discussed and planed to be implemented
as NFC clock provider, but now this series of patches of a common MMC and
NAND sub-clock are never being accepted and the current binding was never
valid. the reasons are:
1. EMMC and NAND, which are mutually exclusive anyway
2. coupling the EMMC and NAND.
3. it seems that a common MMC and NAND sub-clock is over engineered.
and let us see the link for more information:
https://lore.kernel.org/all/[e-mail]
so The meson nfc can't work now, let us rework the clock.

Changes since v4 [5]
 - split the dt binding patch into two patches, one for fixing, 
   clock, the other for coverting to yaml
 - split the nfc driver patch into two patches, one for fixing 
   clock, the other for refining the get nfc resource.

Changes since v3 [4]
 - use devm_platform_ioremap_resource_byname
 - dt_binding_check for mtd/amlogic,meson-nand.yaml

Changes since v2 [3]
 - use fw_name from dts, instead the wrong way using __clk_get_name
 - reg resource size change to 0x800
 - use reg-names

Changes since v1 [2]
 - use clk_parent_data instead of parent_names
 - define a reg resource instead of sd_emmc_c_clkc 

[1] https://lore.kernel.org/r/[e-mail]
    https://lore.kernel.org/r/[e-mail]
[2] https://lore.kernel.org/all/[e-mail]
[3] https://lore.kernel.org/all/[e-mail]
[4] https://lore.kernel.org/all/[e-mail]/

Liang Yang (4):
  dt-bindings: nand: meson: fix meson nfc clock
  mtd: rawnand: meson: fix the clock
  mtd: rawnand: meson: refine resource getting in probe
  dt-bindings: nand: meson: convert txt to yaml

 .../bindings/mtd/amlogic,meson-nand.txt       | 60 -------------
 .../bindings/mtd/amlogic,meson-nand.yaml      | 88 +++++++++++++++++++
 drivers/mtd/nand/raw/meson_nand.c             | 86 +++++++++---------
 3 files changed, 130 insertions(+), 104 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml

Comments

Peter Suti May 31, 2022, 7:08 a.m. UTC | #1

Thank you for the effort for supporting NAND chips on the meson platform!
I'm trying to get our module working with these patch series but 
unfortunately it is not working for me. We are using the A113 and a 
TC58NVG2S0HBAI6 NAND chip.

This NAND chip uses some none ONFI compliant timings which I've set up 
exactly like in the function "th58nvg2s3hbai4_choose_interface_config". 
Even with these timings the chip is not working.

Here are the kernel logs, with some extra logging for the timing parameters:
[    0.981087] loop: module loaded
[    0.981626] megasas: 07.714.04.00-rc1
[    0.984239] nand: device found, Manufacturer ID: 0x98, Chip ID: 0xdc
[    0.988568] nand: Toshiba TC58NVG2S0H 4G 3.3V 8-bit
[    0.993366] nand: 512 MiB, SLC, erase size: 256 KiB, page size: 4096, 
OOB size: 256
[    1.000971] tCLS_min 12000
[    1.003621] tCLH_min 5000
[    1.006223] tCS_min 20000
[    1.008802] tCH_min 5000
[    1.011298] tWP_min 12000
[    1.013891] tALS_min 12000
[    1.016569] tALH_min 5000
[    1.019146] tDS_min 12000
[    1.021739] tDH_min 5000
[    1.024235] tWC_min 25000
[    1.026828] tWH_min 10000
[    1.029415] tWW_min 100000
[    1.032084] tRR_min 20000
[    1.034677] tRP_min 12000
[    1.037264] tRC_min 25000
[    1.039846] tREA_max 20000
[    1.042538] tCEA_max 25000
[    1.045199] tCLR_min 10000
[    1.047868] tAR_min 10000
[    1.050460] tRHOH_min 25000
[    1.053221] tRLOH_min 5000
[    1.055889] tRHZ_max 60000
[    1.058568] tCHZ_max 20000
[    1.061242] tREH_min 10000
[    1.063910] tIR_min 0
[    1.066158] tRHW_min 30000
[    1.068832] tWHR_min 60000
[    1.071500] tWB_max 100000
[    1.074179] tRST_max 500000000
[    1.077198] tPROG_max 700000000
[    1.080303] tBERS_max 5000000000
[    1.083489] tR_max 200000000
[    1.086340] tCCS_min 500000
[    1.089100] tADL_min 400000
[    1.091855] tCEH_min 20000
[    1.094534] tCOH_min 0
[    1.096863] tFEAT_max 1000000
[    1.099791] tITC_max 1000000
[    1.102648] Scanning device for bad blocks
[    1.106898] Bad eraseblock 0 at 0x000000000000
[    1.111653] Bad eraseblock 2 at 0x000000080000
[    1.116045] Bad eraseblock 4 at 0x000000100000
[    1.120445] Bad eraseblock 6 at 0x000000180000
[    1.124844] Bad eraseblock 8 at 0x000000200000
[    1.129242] Bad eraseblock 10 at 0x000000280000
[    1.133728] Bad eraseblock 12 at 0x000000300000
[    1.138212] Bad eraseblock 14 at 0x000000380000
[    1.144153] Bad eraseblock 20 at 0x000000500000
[    1.150824] Bad eraseblock 32 at 0x000000800000
[    1.162579] Bad eraseblock 64 at 0x000001000000
[    1.162780] Bad eraseblock 65 at 0x000001040000
[    1.166144] Bad eraseblock 66 at 0x000001080000
[    1.170630] Bad eraseblock 67 at 0x0000010c0000
[    1.175116] Bad eraseblock 68 at 0x000001100000
[    1.180693] Bad eraseblock 72 at 0x000001200000
[    1.184076] Bad eraseblock 73 at 0x000001240000
[    1.188570] Bad eraseblock 74 at 0x000001280000
[    1.193055] Bad eraseblock 75 at 0x0000012c0000
[    1.197542] Bad eraseblock 76 at 0x000001300000
[    1.203118] Bad eraseblock 80 at 0x000001400000
[    1.206509] Bad eraseblock 81 at 0x000001440000
[    1.210995] Bad eraseblock 82 at 0x000001480000
[    1.215482] Bad eraseblock 83 at 0x0000014c0000
[    1.221422] Bad eraseblock 88 at 0x000001600000
[    1.224443] Bad eraseblock 89 at 0x000001640000
[    1.228935] Bad eraseblock 90 at 0x000001680000
[    1.233421] Bad eraseblock 91 at 0x0000016c0000
...


The bad blocks are reported until the last block is reached.

I added the DTS entries according to the documentation, but had to add 
the all_nand_pins by hand:
mtd_nand: nand-controller@ffe07800 {
     compatible = "amlogic,meson-axg-nfc";
     status = "okay";
     reg = <0x0 0xffe07800 0x0 0x100>, <0x0 0xffe07000 0x0 0x800>;
     reg-names = "nfc", "emmc";
     interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
     clocks = <&clkc CLKID_SD_EMMC_C>,  <&clkc CLKID_FCLK_DIV2>;
     clock-names = "core", "device";

     pinctrl-0 = <&all_nand_pins>;
     pinctrl-names = "default";

     #address-cells = <1>;
     #size-cells = <0>;

     nand@0 {
         reg = <0>;
         nand-ecc-mode = "hw";
     };
};


&pinctrl_periphs {
     all_nand_pins: all_nand_pins {
         mux-0 {
             groups =  "emmc_nand_d0",
                 "emmc_nand_d1",
                 "emmc_nand_d2",
                 "emmc_nand_d3",
                 "emmc_nand_d4",
                 "emmc_nand_d5",
                 "emmc_nand_d6",
                 "emmc_nand_d7",
                 "nand_ce0",
                 "nand_ale",
                 "nand_cle",
                 "nand_wen_clk",
                 "nand_ren_wr",
                 "nand_rb0";
             function = "nand";
             input-enable;
         };
     };
};

Any input on what I'm doing wrong would be appreciated!