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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j8-20020a05600c1c0800b003c6b7f5567csm10325280wms.0.2022.10.21.06.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 06:31:35 -0700 (PDT) Subject: [PATCH v4 0/4] spi: amlogic: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 X-b4-tracking: H4sIACyfUmMC/33NTQrCMBAF4KuUrB1JJrU/rryHuEjSqR2IbUlssJTe3eBS0NXwHrxvNhEpMEVxLj YRKHHkacyhPBTCDWa8E3CXs0CJqKQsYZnBPDz0/II4Mzi0tqa6oUpqkUfWRAIbzOiGPBsX73M5cHxO Yf08SZjP9aeXECRoagy1yqgWTxdrVs820NFND3HLWtL/BZ2Fpu1IYdV3qtJfwr7vb0sgc/P2AAAA From: Amjad Ouled-Ameur Date: Fri, 21 Oct 2022 15:31:24 +0200 Message-Id: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> To: Kevin Hilman , Jerome Brunet , Rob Herring , Martin Blumenstingl , Neil Armstrong , Krzysztof Kozlowski , Mark Brown Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Amjad Ouled-Ameur , Da Xue , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666359095; l=1850; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=uh9b1V5lppXzVxalMWZveFXtfZNKXVHWr9osZJQJmd8=; b=0swTXrE+WS10AzArr7fM6CGstAbhVRX7nQSIOVPrQrbIfFk9podLHQ5iJt+C/00Nj7XVBVPwvjaG BSHMkaSkDAQUMKq8yDVgWMXnURoaBsPi/EI1jLcB/9/tmwrPLfas X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221021_063138_775184_F8B0223A X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message. Signed-off-by: Amjad Ouled-Ameur --- Changes in v4: - Fixed documentation by defining pinctrl-x. - Link to v3: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com Changes in v3: - Fixed documentation by removing pinctrl states as they are not mandatory. - Link to v2: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com --- Amjad Ouled-Ameur (4): spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states spi: meson-spicc: Use pinctrl to drive CLK line when idle arm64: dts: meson-gxl: add SPI pinctrl nodes for CLK arm64: dts: meson-gxbb: add SPI pinctrl nodes for CLK .../bindings/spi/amlogic,meson-gx-spicc.yaml | 75 ++++++++++++++-------- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 14 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 ++++ drivers/spi/spi-meson-spicc.c | 39 ++++++++++- 4 files changed, 113 insertions(+), 29 deletions(-) --- base-commit: e35184f321518acadb681928a016da21a9a20c13 change-id: 20221004-up-aml-fix-spi-c2bb7e78e603 Best regards,