From patchwork Tue Apr 30 06:44:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 13648325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDBE4C4345F for ; Tue, 30 Apr 2024 06:45:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=uAKtOG7cOWMwmoT1+RWyaT1UgOIALVFNe2j1gLvAKo0=; b=Zo2Cg8TutBalcQ mJURCATyEWeK52jSVpxLcNIQcwGv+/6SEPFJ/IUDU69psvLTWI8VopdWJJipZoEa3eFIrKlCJFBJL Di4y14DoBtux+0HsW3xCIJmCbDDuz6RZLCot6eLV2RThHua5aksm8KTqHmhBMa6+bpKVoHH1heJBt jfDPVMKuYJV650v+E/JCd3F02IMbwe2bmWrwNauP4NIamu5C4J5IPG6vpnKvhDCzCedszBXbXW5Ch 2hEE6RSe2ASxrvZnNA8LXtGJj75VcjMCcFLmhrS5aCzclyjzKrwqknXsEu0UUltlnrdKEj6luQxDL jVqAhwg5y3tEBVcaewMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1hEs-00000005K3P-0g8k; Tue, 30 Apr 2024 06:45:18 +0000 Received: from [58.32.228.46] (helo=mail-sh.amlogic.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1hEo-00000005Jzr-3uDh; Tue, 30 Apr 2024 06:45:16 +0000 Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.6; Tue, 30 Apr 2024 14:44:42 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Xianwei Zhao Subject: [PATCH v8 0/5] Add C3 SoC PLLs and Peripheral clock Date: Tue, 30 Apr 2024 14:44:33 +0800 Message-ID: <20240430064438.2094701-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_234515_226321_43C2588E X-CRM114-Status: GOOD ( 10.62 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Changes since V7 [1]: - Remove included head file not used. - Link to v7: https://lore.kernel.org/all/20240424050928.1997820-1-xianwei.zhao@amlogic.com Changes since V6 [12]: - Add pad src for rtc clock. - Add SCMI clock controller support, move some clock node in SCMI,such as GP1 PLL DDR USB etc. - Fix some spelling mistake. - Use lower case for bindings and update some input clocks desc. - Update some clock comments. - Delete prefix "AML_" for macro definition. - Addd some clock annotation and some clock flag CRITICAL. - Add maximum for regmap_config. - Delete some unused register definition and unused clock inputs. - Drop patch subject redundant "bindings". Suggested by Krzysztof. - Not reference header file "clk.h" and replace comment. Suggested by Jerome. - Modify description about board in Kconfig file help item. Suggested by Jerome. - Link to v6: https://lore.kernel.org/all/20231106085554.3237511-1-xianwei.zhao@amlogic.com Changes since V5 [3]: - Fix some typo and modify formart for MARCO. Suggested by Jerome. - Add pad clock for peripheral input clock in bindings. - Add some description for explaining why ddr_dpll_pt_clk and cts_msr_clk are out of tree. Changes since V4 [10]: - Change some fw_name of clocks. Suggested by Jerome. - Delete minItem of clocks. - Add CLk_GET_RATE_NOCACHE flags for gp1_pll - Fix some format. and fix width as 8 for mclk_pll_dco. - exchange gate and divder for fclk_50m clock. - add CLK_SET_RATE_PARENT for axi_a_divder & axi_b_divder. - add CLK_IS_CRITICAL for axi_clk - Optimized macro define for pwm clk. - add cts_oscin_clk mux between 24M and 32k - add some missing gate clock, such as ddr_pll. Changes since V3 [7]: - Modify Kconfig desc and PLL yaml clk desc. - Fix some format.Suggested by Yixun and Jerome. - Add flag CLK_GET_RATE_NOCACHE for sys_clk. - Optimized macro define for pwm clk. - Use flag CLK_IS_CRITICAL for axi_clk. - Add some description for some clocks. - Use FCLK_50M instead of FCLK_DIV40. Changes since V2 [4]: - Modify some format, include clk name & inline, and so on. - Define marco for pwm clock. - Add GP1_PLL clock. - Modify yaml use raw instead of macro. Changes since V1 [2]: - Fix errors when check binding by using "make dt_binding_check". - Delete macro definition. Xianwei Zhao (5): dt-bindings: clock: add Amlogic C3 PLL clock controller dt-bindings: clock: add Amlogic C3 SCMI clock controller support dt-bindings: clock: add Amlogic C3 peripherals clock controller clk: meson: c3: add support for the C3 SoC PLL clock clk: meson: c3: add c3 clock peripherals controller driver .../clock/amlogic,c3-peripherals-clkc.yaml | 120 + .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 + drivers/clk/meson/Kconfig | 29 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/c3-peripherals.c | 2365 +++++++++++++++++ drivers/clk/meson/c3-pll.c | 746 ++++++ .../clock/amlogic,c3-peripherals-clkc.h | 212 ++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 40 + .../dt-bindings/clock/amlogic,c3-scmi-clkc.h | 27 + 9 files changed, 3600 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml create mode 100644 drivers/clk/meson/c3-peripherals.c create mode 100644 drivers/clk/meson/c3-pll.c create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,c3-scmi-clkc.h base-commit: ba535bce57e71463a86f8b33a0ea88c26e3a6418