Show patches with: Submitter = Yixun Lan       |    Archived = No       |   216 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[3/4] pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC - 1 - --- 2017-11-08 Yixun Lan Superseded
[2/4] pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC - 1 - --- 2017-11-08 Yixun Lan Superseded
[1/4] documentation: Add compatibles for Amlogic Meson AXG pin controllers - 1 - --- 2017-11-08 Yixun Lan Superseded
[v4,1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA - - 1 --- 2017-11-07 Yixun Lan Accepted
[v4,4/4] ARM64: dts: meson: drop "sana" clock from SAR ADC 1 - - --- 2017-11-07 Yixun Lan Accepted
[v4,3/4] dt-bindings: iio: adc: update the doc for SAR ADC 1 - - --- 2017-11-07 Yixun Lan Accepted
[v4,2/4] iio: adc: meson-saradc: remove irrelevant clock "sana" - 1 - --- 2017-11-07 Yixun Lan Accepted
[v3,1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA - - 1 --- 2017-11-07 Yixun Lan Superseded
[v3,4/4] ARM64: dts: meson: drop "sana" clock from SARADC - - - --- 2017-11-07 Yixun Lan Superseded
[v3,4/4] ARM64: dts: meson: drop "sana" clock from SAR ADC - - - --- 2017-11-07 Yixun Lan Superseded
[v3,3/4] dt-bindings: iio: adc: update the doc for SAR ADC 1 - - --- 2017-11-07 Yixun Lan Superseded
[v3,2/4] iio: adc: meson-saradc: remove irrelevant clock "sana" - - - --- 2017-11-07 Yixun Lan Superseded
clk: meson: gxbb: fix wrong clock for SARADC/SANA - - 1 --- 2017-11-06 Yixun Lan Superseded
[2/2] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC - - - --- 2017-11-06 Yixun Lan Superseded
[1/2] clk: meson-axg: add clock controller drivers - - - --- 2017-11-06 Yixun Lan Superseded
clk: meson: gxbb: fix wrong clock for SARADC - - - --- 2017-11-03 Yixun Lan Rejected
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