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Fri, 07 Sep 2018 12:42:24 -0700 (PDT) From: Corentin Labbe To: Gilles.Muller@lip6.fr, Julia.Lawall@lip6.fr, agust@denx.de, alexandre.torgue@st.com, alistair@popple.id.au, benh@kernel.crashing.org, carlo@caione.org, davem@davemloft.net, galak@kernel.crashing.org, joabreu@synopsys.com, khilman@baylibre.com, maxime.ripard@bootlin.com, michal.lkml@markovi.net, mpe@ellerman.id.au, mporter@kernel.crashing.org, nicolas.palix@imag.fr, oss@buserror.net, paulus@samba.org, peppe.cavallaro@st.com, tj@kernel.org, vitb@kernel.crashing.org, wens@csie.org Subject: [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions Date: Fri, 7 Sep 2018 19:41:47 +0000 Message-Id: <1536349307-20714-6-git-send-email-clabbe@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com> References: <1536349307-20714-1-git-send-email-clabbe@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180907_124235_801985_E3A72911 X-CRM114-Status: GOOD ( 12.05 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe , linux-amlogic@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, cocci@systeme.lip6.fr, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch converts ahci_sunxi to use xxxsetbits32 functions Signed-off-by: Corentin Labbe --- drivers/ata/ahci_sunxi.c | 51 ++++++++++++------------------------------------ 1 file changed, 12 insertions(+), 39 deletions(-) diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index 911710643305..0799441f1237 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ahci.h" #define DRV_NAME "ahci-sunxi" @@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp, #define AHCI_P0PHYCR 0x0178 #define AHCI_P0PHYSR 0x017c -static void sunxi_clrbits(void __iomem *reg, u32 clr_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val &= ~(clr_val); - writel(reg_val, reg); -} - -static void sunxi_setbits(void __iomem *reg, u32 set_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val |= set_val; - writel(reg_val, reg); -} - -static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val &= ~(clr_val); - reg_val |= set_val; - writel(reg_val, reg); -} - static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) { return (readl(reg) >> shift) & mask; @@ -100,22 +73,22 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) writel(0, reg_base + AHCI_RWCR); msleep(5); - sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, + setbits32(reg_base + AHCI_PHYCS1R, BIT(19)); + clrsetbits32(reg_base + AHCI_PHYCS0R, (0x7 << 24), (0x5 << 24) | BIT(23) | BIT(18)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, + clrsetbits32(reg_base + AHCI_PHYCS1R, (0x3 << 16) | (0x1f << 8) | (0x3 << 6), (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); - sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); - sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, + setbits32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); + clrbits32(reg_base + AHCI_PHYCS1R, BIT(19)); + clrsetbits32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, + clrsetbits32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); msleep(5); - sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + setbits32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); timeout = 250; /* Power up takes aprox 50 us */ do { @@ -130,7 +103,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) udelay(1); } while (1); - sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + setbits32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); timeout = 100; /* Calibration takes aprox 10 us */ do { @@ -158,10 +131,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap) struct ahci_host_priv *hpriv = ap->host->private_data; /* Setup DMA before DMA start */ - sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); + clrsetbits32(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); /* Start DMA */ - sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); + setbits32(port_mmio + PORT_CMD, PORT_CMD_START); } static const struct ata_port_info ahci_sunxi_port_info = {