| Message ID | 1545120286-129258-2-git-send-email-hanjie.lin@amlogic.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | add the Amlogic Meson PCIe controller driver | expand |
Hi Rob, Hi Hanjie, (sorry for being late with my question) On Tue, Dec 18, 2018 at 9:05 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote: [...] > +- reg-names: Must be > + - "elbi" External local bus interface registers > + - "cfg" Meson specific registers > + - "phy" Meson PCIE PHY registers I have learned that there are two PHY register designs: - AXG only has a PCIe PHY - G12A has a PHY which supports PCIe and USB 3.0. The PCIe part of this PHY design is compatible with AXG, but this design also supports a USB 3.0 port (it's an exclusive choice: either PCIe *or* USB 3.0) The PCIe controller itself is identical on both, AXG and G12A. This patch adds support for the AXG PCIe controller and PHY within one device-tree node. For G12A I propose to add a separate "phys" property with a phandle to the "combo" PCIe and USB3.0 PHY - this can be part of a separate patch though. I would like to know whether it's OK that for AXG the PCIe PHY is described in the same device-tree node as the PCIe controller (in other words: we're not using a "phys" property here)? Kind Regards Martin
On 2018/12/19 7:14, Martin Blumenstingl wrote: > Hi Rob, Hi Hanjie, > > (sorry for being late with my question) > > On Tue, Dec 18, 2018 at 9:05 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote: > [...] >> +- reg-names: Must be >> + - "elbi" External local bus interface registers >> + - "cfg" Meson specific registers >> + - "phy" Meson PCIE PHY registers > I have learned that there are two PHY register designs: > - AXG only has a PCIe PHY > - G12A has a PHY which supports PCIe and USB 3.0. The PCIe part of > this PHY design is compatible with AXG, but this design also supports > a USB 3.0 port (it's an exclusive choice: either PCIe *or* USB 3.0) > > The PCIe controller itself is identical on both, AXG and G12A. > This patch adds support for the AXG PCIe controller and PHY within one > device-tree node. > > For G12A I propose to add a separate "phys" property with a phandle to > the "combo" PCIe and USB3.0 PHY - this can be part of a separate patch > though. > I would like to know whether it's OK that for AXG the PCIe PHY is > described in the same device-tree node as the PCIe controller (in > other words: we're not using a "phys" property here)? > > > Kind Regards > Martin > > . > hi matrin, We do had a dedicated PHY driver for a time at the begining of this patch series, but we decided to remove it and integrate into the controller driver after series reviews and disscussions, and the main reason is it's too overkill to have a dedicated PHY driver which only do the RESET job. Of course we can consider the dedicated PHY driver for G12A upstream in future. thanks hanjie
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt new file mode 100644 index 0000000..12b18f8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -0,0 +1,70 @@ +Amlogic Meson AXG DWC PCIE SoC controller + +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. +It shares common functions with the PCIe DesignWare core driver and +inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties: +- compatible: + should contain "amlogic,axg-pcie" to identify the core. +- reg: + should contain the configuration address space. +- reg-names: Must be + - "elbi" External local bus interface registers + - "cfg" Meson specific registers + - "phy" Meson PCIE PHY registers + - "config" PCIe configuration space +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: Must include the following entries: + - "pclk" PCIe GEN 100M PLL clock + - "port" PCIe_x(A or B) RC clock gate + - "general" PCIe Phy clock + - "mipi" PCIe_x(A or B) 100M ref clock gate +- resets: phandle to the reset lines. +- reset-names: must contain "phy" "port" and "apb" + - "phy" Share PHY reset + - "port" Port A or B reset + - "apb" Share APB reset +- device_type: + should be "pci". As specified in designware-pcie.txt + + +Example configuration: + + pcie: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xf9800000 0x0 0x400000 + 0x0 0xff646000 0x0 0x2000 + 0x0 0xff644000 0x0 0x2000 + 0x0 0xf9f00000 0x0 0x100000>; + reg-names = "elbi", "cfg", "phy", "config"; + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; + + clocks = <&clkc CLKID_USB + &clkc CLKID_MIPI_ENABLE + &clkc CLKID_PCIE_A + &clkc CLKID_PCIE_CML_EN0>; + clock-names = "general", + "mipi", + "pclk", + "port"; + resets = <&reset RESET_PCIE_PHY>, + <&reset RESET_PCIE_A>, + <&reset RESET_PCIE_APB>; + reset-names = "phy", + "port", + "apb"; + };