Message ID | 1582204512-7582-1-git-send-email-nbelin@baylibre.com (mailing list archive) |
---|---|
State | Mainlined |
Commit | dc7a06b0dbbafac8623c2b7657e61362f2f479a7 |
Headers | show |
Series | [RESEND] pinctrl: meson-gxl: fix GPIOX sdio pins | expand |
On Thu, Feb 20, 2020 at 2:15 PM Nicolas Belin <nbelin@baylibre.com> wrote: > In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused > any issue so far because devices using these pins always take both pins > so the resulting configuration is OK. > > Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") > Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Nicolas Belin <nbelin@baylibre.com> Patch applied! Yours, Linus Walleij
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 1b6e8646700f..2ac921c83da9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; -static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; static const unsigned int nand_ce0_pins[] = { BOOT_8 };