From patchwork Fri Nov 25 13:01:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 9447517 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 016DA60778 for ; Fri, 25 Nov 2016 13:04:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E609A2756B for ; Fri, 25 Nov 2016 13:04:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA85627FAD; Fri, 25 Nov 2016 13:04:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8B5BF28047 for ; Fri, 25 Nov 2016 13:04:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cAGBC-0006R9-3y; Fri, 25 Nov 2016 13:04:38 +0000 Received: from mail-wj0-x243.google.com ([2a00:1450:400c:c01::243]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cAG9R-0004Qs-72; Fri, 25 Nov 2016 13:03:00 +0000 Received: by mail-wj0-x243.google.com with SMTP id xy5so5534272wjc.1; Fri, 25 Nov 2016 05:02:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4z0kqFvyl6cY0siiMG8OAF77n2+sCFVcb5h9mn8eN4U=; b=BnetjhEITg01n7LvTV34B8FwmZSwwCIsI8qPo0Wh2Q04B5IWTojznyxklyzvDJONuI BaG8Y4WoGsE/i+k2avAl1FbYv2/6pTp0sXoNGI6SH43/Elp2Q2c+DZZiWWXnR7oInr+/ z22dRHh+0MmXOM5QJehu/sdbUB7uNLvi8+JkegUiWBEN1t66NyYW7xALIS9k/GDJt21S uYjsKaskl35dOKPZRdQ2JMXEl32kboRTpIOTdLs2Ln5WDfVNlWXWh7Ylaamyzh3bmqCy t8NmZRrprpXVdWsCaB8B/Xbt8Kz8Bc0XtFRYsPlNRAkW4n9ttBql7Q5SYW3F/hkzFL9k Zj1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4z0kqFvyl6cY0siiMG8OAF77n2+sCFVcb5h9mn8eN4U=; b=cFPasorc/bal7XyTHYc0BEKb19ptCfnUG6mx5rdz+58uq3EHBj3vOos/sOoLF3DOMt HhtjcFpJ/S7d8snM84COiS8O96W+cKMD2qw3J2qCjCMuQEmfpK/KGciS7ucgB+gRkpBE t3Jm2ZunDyoH/TTGhz7bBaEyb4DdRynLWjbvnVcLhXb+8uiWVE0Y8JvKlztghEc8asyF wapD/BVN0dVCChjCWFmAipLrCkvt11tb7C0zfoJt3yqcf0puYJTD9xi4iPFmbLm6Mbh9 iiK4hX0yeGF9+x6GWv1nxIEcskEeefhxtYq9Sg47Cg1BAq7s4qxF4XAX/ybtsl89FdLL Vl+A== X-Gm-Message-State: AKaTC019lOdxW/HYmZLikvQ9pc2T22zPPTuiuXY0hvPA8TWwGKd4aG2wSbgQu6VwU8MJbA== X-Received: by 10.195.18.71 with SMTP id gk7mr8484445wjd.175.1480078947231; Fri, 25 Nov 2016 05:02:27 -0800 (PST) Received: from blackbox.darklights.net ([2003:dc:d3d3:9204:9426:48db:352f:a6de]) by smtp.googlemail.com with ESMTPSA id ua15sm46937433wjb.1.2016.11.25.05.02.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Nov 2016 05:02:26 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, davem@davemloft.net, khilman@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org Subject: [PATCH v2 2/7] net: stmmac: dwmac-meson8b: make the RGMII TX delay configurable Date: Fri, 25 Nov 2016 14:01:51 +0100 Message-Id: <20161125130156.17879-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161125130156.17879-1-martin.blumenstingl@googlemail.com> References: <20161124143417.10178-1-martin.blumenstingl@googlemail.com> <20161125130156.17879-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161125_050249_661310_C73D7F98 X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f.fainelli@gmail.com, alexandre.torgue@st.com, Martin Blumenstingl , catalin.marinas@arm.com, will.deacon@arm.com, carlo@caione.org, peppe.cavallaro@st.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Prior to this patch we were using a hardcoded RGMII TX clock delay of 2ns (= 1/4 cycle of the 125MHz RGMII TX clock). This value works for many boards, but unfortunately not for all (due to the way the actual circuit is designed, sometimes because the TX delay is enabled in the PHY, etc.). Making the TX delay on the MAC side configurable allows us to support all possible hardware combinations. This allows fixing a compatibility issue on some boards, where the RTL8211F PHY is configured to generate the TX delay. We can now turn off the TX delay in the MAC, because otherwise we would be applying the delay twice (which results in non-working TX traffic). Signed-off-by: Martin Blumenstingl --- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 26 +++++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 250e4ce..8ba33be 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -35,10 +35,6 @@ #define PRG_ETH0_TXDLY_SHIFT 5 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) -#define PRG_ETH0_TXDLY_OFF (0x0 << PRG_ETH0_TXDLY_SHIFT) -#define PRG_ETH0_TXDLY_QUARTER (0x1 << PRG_ETH0_TXDLY_SHIFT) -#define PRG_ETH0_TXDLY_HALF (0x2 << PRG_ETH0_TXDLY_SHIFT) -#define PRG_ETH0_TXDLY_THREE_QUARTERS (0x3 << PRG_ETH0_TXDLY_SHIFT) /* divider for the result of m250_sel */ #define PRG_ETH0_CLK_M250_DIV_SHIFT 7 @@ -69,6 +65,8 @@ struct meson8b_dwmac { struct clk_divider m25_div; struct clk *m25_div_clk; + + u32 tx_delay_ns; }; static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, @@ -179,6 +177,7 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; unsigned long clk_rate; + u8 tx_dly_val; switch (dwmac->phy_mode) { case PHY_INTERFACE_MODE_RGMII: @@ -196,9 +195,13 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_INVERTED_RMII_CLK, 0); - /* TX clock delay - all known boards use a 1/4 cycle delay */ + /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where + * 8ns are exactly one cycle of the 125MHz RGMII TX clock): + * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3 + */ + tx_dly_val = dwmac->tx_delay_ns >> 1; meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, - PRG_ETH0_TXDLY_QUARTER); + tx_dly_val << PRG_ETH0_TXDLY_SHIFT); break; case PHY_INTERFACE_MODE_RMII: @@ -277,6 +280,17 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) if (dwmac->phy_mode < 0) { dev_err(&pdev->dev, "missing phy-mode property\n"); return -EINVAL; + } else if (dwmac->phy_mode != PHY_INTERFACE_MODE_RMII) { + ret = of_property_read_u32(pdev->dev.of_node, + "amlogic,tx-delay-ns", + &dwmac->tx_delay_ns); + if (ret && dwmac->phy_mode == PHY_INTERFACE_MODE_RGMII) + /* default to a TX clock delay of 2ns when the PHY is + * connected via RGMII (with RGMII_ID and RGMII_TXID + * the TX clock delay is generated by the PHY and thus + * we use the default 0ns delay in these case). + */ + dwmac->tx_delay_ns = 2; } ret = meson8b_init_clk(dwmac);