diff mbox

ARM64: dts: meson-axg: add RMII pins for ethernet controller

Message ID 20180111030411.197054-1-yixun.lan@amlogic.com (mailing list archive)
State Accepted
Headers show

Commit Message

Yixun Lan Jan. 11, 2018, 3:04 a.m. UTC
Comparing to RGMII interface, the RMII interface require few pins.
So it's worth describing them here.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Comments

Jerome Brunet Jan. 11, 2018, 8:37 a.m. UTC | #1
On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
> Comparing to RGMII interface, the RMII interface require few pins.
> So it's worth describing them here.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>

The only axg platform we have upstream is the s400 and is using rgmii.
May I ask how this was tested ?
Yixun Lan Jan. 11, 2018, 9:11 a.m. UTC | #2
Hi Jerome:

On 01/11/18 16:37, Jerome Brunet wrote:
> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>> Comparing to RGMII interface, the RMII interface require few pins.
>> So it's worth describing them here.
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> 
> The only axg platform we have upstream is the s400 and is using rgmii.
> May I ask how this was tested ?
> 
It's true that S400 using RGMII interface.

but, we have customer using RTL8201FR-VB/VD which is a RMII PHY,

This is actually tested with the 'eth_rmii_x_pins' group.

Yixun
Neil Armstrong Jan. 11, 2018, 9:33 a.m. UTC | #3
On 11/01/2018 10:11, Yixun Lan wrote:
> Hi Jerome:
> 
> On 01/11/18 16:37, Jerome Brunet wrote:
>> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>>> Comparing to RGMII interface, the RMII interface require few pins.
>>> So it's worth describing them here.
>>>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>
>> The only axg platform we have upstream is the s400 and is using rgmii.
>> May I ask how this was tested ?
>>
> It's true that S400 using RGMII interface.
> 
> but, we have customer using RTL8201FR-VB/VD which is a RMII PHY,
> 
> This is actually tested with the 'eth_rmii_x_pins' group.
> 
> Yixun
> 

I pushed the same for GXBB,

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Kevin Hilman Jan. 31, 2018, midnight UTC | #4
Neil Armstrong <narmstrong@baylibre.com> writes:

> On 11/01/2018 10:11, Yixun Lan wrote:
>> Hi Jerome:
>> 
>> On 01/11/18 16:37, Jerome Brunet wrote:
>>> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>>>> Comparing to RGMII interface, the RMII interface require few pins.
>>>> So it's worth describing them here.
>>>>
>>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>>
>>> The only axg platform we have upstream is the s400 and is using rgmii.
>>> May I ask how this was tested ?
>>>
>> It's true that S400 using RGMII interface.
>> 
>> but, we have customer using RTL8201FR-VB/VD which is a RMII PHY,
>> 
>> This is actually tested with the 'eth_rmii_x_pins' group.
>> 
>> Yixun
>> 
>
> I pushed the same for GXBB,
>
> Acked-by: Neil Armstrong <narmstrong@baylibre.com>

Applied to v4.17/dt64 with Neil's ack.

Kevin
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..ab4a0e8bc446 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -251,6 +251,36 @@ 
 					gpio-ranges = <&pinctrl_periphs 0 0 86>;
 				};
 
+				eth_rmii_x_pins: eth-x-rmii {
+					mux {
+						groups = "eth_mdio_x",
+						       "eth_mdc_x",
+						       "eth_rgmii_rx_clk_x",
+						       "eth_rx_dv_x",
+						       "eth_rxd0_x",
+						       "eth_rxd1_x",
+						       "eth_txen_x",
+						       "eth_txd0_x",
+						       "eth_txd1_x";
+						function = "eth";
+					};
+				};
+
+				eth_rmii_y_pins: eth-y-rmii {
+					mux {
+						groups = "eth_mdio_y",
+						       "eth_mdc_y",
+						       "eth_rgmii_rx_clk_y",
+						       "eth_rx_dv_y",
+						       "eth_rxd0_y",
+						       "eth_rxd1_y",
+						       "eth_txen_y",
+						       "eth_txd0_y",
+						       "eth_txd1_y";
+						function = "eth";
+					};
+				};
+
 				eth_rgmii_x_pins: eth-x-rgmii {
 					mux {
 						groups = "eth_mdio_x",