From patchwork Tue Jul 10 16:36:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 10516539 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6234F600CA for ; Tue, 10 Jul 2018 08:41:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C3E9283A8 for ; Tue, 10 Jul 2018 08:41:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3FEFF2808F; Tue, 10 Jul 2018 08:41:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78404283A8 for ; Tue, 10 Jul 2018 08:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yWF9wycZMr6ugxtQgAT+s2M3eOibnVVPqDkxxng/cL4=; b=Khw0aEMHKL2uGC 2oghqnNafYxGbBuaFMy1Y7rBsSMf3hgs0Yv/OoCRwscsp5EG/jRxdAzNPkfOw1ckYMQ9biSMeoqEz HuM/1OXMTFToE7OrklOva6/iI08NMXJTa+pz8WvBBhDYx1ATMbz4Jv+JZpZ3JgZnE+ZphecVr7EBv TFbQydmE6JeSVviSpqQe+FsFV3MegPhi9GMPqWicyq7WZzSSDXtuGo3qp/5nLh045fHOxU07Pj5LL z7u2FiEYeIW4pvEyNnpY3LUXrW/JS9YXK/HPva+ignlq/SlAmRvOOu0+Ewif/7DuTiIS4VPpvhYvP fzxo2gWq8B203QYVyEoA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fcoDO-000218-Ib; Tue, 10 Jul 2018 08:41:42 +0000 Received: from mail-sh2.amlogic.com ([58.32.228.45]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fcoCw-0001S3-Vt; Tue, 10 Jul 2018 08:41:30 +0000 Received: from localhost.localdomain (10.18.20.250) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Tue, 10 Jul 2018 16:39:25 +0800 From: Yixun Lan To: Jerome Brunet , Neil Armstrong Subject: [PATCH v2 3/3] clk: meson: add sub MMC clock controller driver Date: Tue, 10 Jul 2018 16:36:58 +0000 Message-ID: <20180710163658.6175-4-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180710163658.6175-1-yixun.lan@amlogic.com> References: <20180710163658.6175-1-yixun.lan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.20.250] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180710_014115_685338_5A715569 X-CRM114-Status: GOOD ( 18.99 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Stephen Boyd , Kevin Hilman , Michael Turquette , Yixun Lan , linux-kernel@vger.kernel.org, Boris Brezillon , Liang Yang , Qiufang Dai , Miquel Raynal , Carlo Caione , linux-amlogic@lists.infradead.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jian Hu Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The patch will add a MMC clock controller driver which used by MMC or NAND, It provide a mux and divider clock, and three phase clocks - core, tx, tx. Two clocks are provided as the parent of MMC clock controller from upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform. To specify which clock the MMC or NAND driver may consume, the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header can be used in the device tree sources. Signed-off-by: Yixun Lan --- drivers/clk/meson/Kconfig | 9 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/mmc-clkc.c | 419 +++++++++++++++++++++++++++++++++++ 3 files changed, 429 insertions(+) create mode 100644 drivers/clk/meson/mmc-clkc.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index efaa70f682b4..edc18e65c89b 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -15,6 +15,15 @@ config COMMON_CLK_MESON_AO select COMMON_CLK_REGMAP_MESON select RESET_CONTROLLER +config COMMON_CLK_MMC_MESON + tristate "Meson MMC Sub Clock Controller Driver" + depends on COMMON_CLK_AMLOGIC + select MFD_SYSCON + select REGMAP + help + Support for the MMC sub clock controller on Amlogic Meson Platform, + Say Y if you want this clock enabled. + config COMMON_CLK_REGMAP_MESON bool select REGMAP diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 72ec8c40d848..4b3817f80ba1 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o +obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c new file mode 100644 index 000000000000..43b7a376746d --- /dev/null +++ b/drivers/clk/meson/mmc-clkc.c @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson MMC Sub Clock Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yixun Lan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clkc.h" + +/* clock ID used by internal driver */ +#define CLKID_MMC_MUX 0 +#define CLKID_MMC_PHASE_CORE 2 + +#define SD_EMMC_CLOCK 0 +#define CLK_DIV_MASK GENMASK(5, 0) +#define CLK_SRC_MASK GENMASK(7, 6) +#define CLK_CORE_PHASE_MASK GENMASK(9, 8) +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12) +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) +#define CLK_V2_ALWAYS_ON BIT(24) + +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) +#define CLK_V3_ALWAYS_ON BIT(28) + +#define CLK_DELAY_STEP_PS 200 +#define CLK_PHASE_STEP 30 +#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) + +#define MUX_CLK_NUM_PARENTS 2 +#define MMC_MAX_CLKS 5 + +struct clk_regmap_phase_data { + unsigned long phase_mask; + unsigned long delay_mask; + unsigned int delay_step_ps; +}; + +struct mmc_clkc_data { + struct clk_regmap_phase_data tx; + struct clk_regmap_phase_data rx; +}; + +struct mmc_clkc_info { + struct device *dev; + struct regmap *map; + struct mmc_clkc_data *data; +}; + +static inline struct clk_regmap_phase_data * +clk_get_regmap_phase_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_phase_data *)clk->data; +} + +static struct clk_regmap_mux_data mmc_clkc_mux_data = { + .offset = SD_EMMC_CLOCK, + .mask = 0x3, + .shift = 6, + .flags = CLK_DIVIDER_ROUND_CLOSEST, +}; + +static struct clk_regmap_div_data mmc_clkc_div_data = { + .offset = SD_EMMC_CLOCK, + .shift = 0, + .width = 6, + .flags = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED, +}; + +static struct clk_regmap_phase_data mmc_clkc_core_phase = { + .phase_mask = CLK_CORE_PHASE_MASK, +}; + +static const struct mmc_clkc_data mmc_clkc_gx_data = { + { + .phase_mask = CLK_TX_PHASE_MASK, + .delay_mask = CLK_V2_TX_DELAY_MASK, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, + { + .phase_mask = CLK_RX_PHASE_MASK, + .delay_mask = CLK_V2_RX_DELAY_MASK, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, +}; + +static const struct mmc_clkc_data mmc_clkc_axg_data = { + { + .phase_mask = CLK_TX_PHASE_MASK, + .delay_mask = CLK_V3_TX_DELAY_MASK, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, + { + .phase_mask = CLK_RX_PHASE_MASK, + .delay_mask = CLK_V3_RX_DELAY_MASK, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, +}; + +static const struct of_device_id mmc_clkc_match_table[] = { + { + .compatible = "amlogic,meson-gx-mmc-clkc", + .data = &mmc_clkc_gx_data + }, + { + .compatible = "amlogic,meson-axg-mmc-clkc", + .data = &mmc_clkc_axg_data + }, + {} +}; +MODULE_DEVICE_TABLE(of, mmc_clkc_match_table); + +static struct clk_regmap *mmc_clkc_register_mux(struct mmc_clkc_info *clkc) +{ + const char *parent_names[MUX_CLK_NUM_PARENTS]; + struct device *dev = clkc->dev; + struct clk_init_data init; + struct clk_regmap *mux; + struct clk *clk; + char *mux_name; + int i, ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { + char name[8]; + + snprintf(name, sizeof(name), "clkin%d", i); + clk = devm_clk_get(dev, name); + if (IS_ERR(clk)) { + if (clk != ERR_PTR(-EPROBE_DEFER)) + dev_err(dev, "Missing clock %s\n", name); + return ERR_PTR((long)clk); + } + + parent_names[i] = __clk_get_name(clk); + } + + mux_name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev)); + if (!mux_name) + return ERR_PTR(-ENOMEM); + + mux->map = clkc->map; + mux->data = &mmc_clkc_mux_data; + + init.name = mux_name; + init.ops = &clk_regmap_mux_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = parent_names; + init.num_parents = MUX_CLK_NUM_PARENTS; + + mux->hw.init = &init; + ret = devm_clk_hw_register(dev, &mux->hw); + if (ret) { + dev_err(dev, "Mux clock registration failed\n"); + mux = ERR_PTR(ret); + } + + kfree(mux_name); + return mux; +} + +static struct clk_regmap *mmc_clkc_register_div(struct mmc_clkc_info *clkc) +{ + const char *parent_names[MUX_CLK_NUM_PARENTS]; + struct device *dev = clkc->dev; + struct clk_init_data init; + struct clk_regmap *div; + char *mux_name, *div_name; + int ret; + + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + mux_name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev)); + div_name = kasprintf(GFP_KERNEL, "%s#div", dev_name(dev)); + if (!mux_name || !div_name) { + div = ERR_PTR(-ENOMEM); + goto err; + } + + parent_names[0] = mux_name; + div->map = clkc->map; + div->data = &mmc_clkc_div_data; + + init.name = div_name; + init.ops = &clk_regmap_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = parent_names; + init.num_parents = 1; + + div->hw.init = &init; + ret = devm_clk_hw_register(dev, &div->hw); + if (ret) { + dev_err(dev, "Divider clock registration failed\n"); + div = ERR_PTR(ret); + } + +err: + kfree(mux_name); + kfree(div_name); + return div; +} + +static int clk_regmap_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_phase_data *ph = clk_get_regmap_phase_data(clk); + unsigned int phase_num = 1 << hweight_long(ph->phase_mask); + unsigned long period_ps, p, d; + int degrees; + u32 val; + + regmap_read(clk->map, SD_EMMC_CLOCK, &val); + p = (val & ph->phase_mask) >> __ffs(ph->phase_mask); + degrees = p * 360 / phase_num; + + if (ph->delay_mask) { + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_get_rate(hw->clk)); + d = (val & ph->delay_mask) >> __ffs(ph->delay_mask); + degrees += d * ph->delay_step_ps * 360 / period_ps; + degrees %= 360; + } + + return degrees; +} + +static void clk_regmap_apply_phase_delay(struct clk_regmap *clk, + unsigned int phase, + unsigned int delay) +{ + struct clk_regmap_phase_data *ph = clk->data; + u32 val; + + regmap_read(clk->map, SD_EMMC_CLOCK, &val); + + val &= ~ph->phase_mask; + val |= phase << __ffs(ph->phase_mask); + + if (ph->delay_mask) { + val &= ~ph->delay_mask; + val |= delay << __ffs(ph->delay_mask); + } + + regmap_write(clk->map, SD_EMMC_CLOCK, val); +} + +static int clk_regmap_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_phase_data *ph = clk_get_regmap_phase_data(clk); + unsigned int phase_num = 1 << hweight_long(ph->phase_mask); + unsigned long period_ps, d = 0, r; + u64 p; + + p = degrees % 360; + + if (!ph->delay_mask) { + p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); + } else { + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_get_rate(hw->clk)); + + /* First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + r = do_div(p, 360 / phase_num); + d = DIV_ROUND_CLOSEST(r * period_ps, + 360 * ph->delay_step_ps); + d = min(d, ph->delay_mask >> __ffs(ph->delay_mask)); + } + + clk_regmap_apply_phase_delay(clk, p, d); + return 0; +} + +static const struct clk_ops clk_regmap_phase_ops = { + .get_phase = clk_regmap_get_phase, + .set_phase = clk_regmap_set_phase, +}; + +static struct clk_regmap * +mmc_clkc_register_phase_clk(struct mmc_clkc_info *clkc, + char *name, char *parent_name, unsigned long flags, + struct clk_regmap_phase_data *phase_data) + +{ + const char *parent_names[MUX_CLK_NUM_PARENTS]; + struct device *dev = clkc->dev; + struct clk_init_data init; + struct clk_regmap *x; + char *clk_name, *core_name; + int ret; + + /* create the mmc rx clock */ + x = devm_kzalloc(dev, sizeof(*x), GFP_KERNEL); + if (!x) + return ERR_PTR(-ENOMEM); + + clk_name = kasprintf(GFP_KERNEL, "%s#%s", dev_name(dev), name); + core_name = kasprintf(GFP_KERNEL, "%s#%s", dev_name(dev), parent_name); + + if (!clk_name || !core_name) { + x = ERR_PTR(-ENOMEM); + goto err; + } + parent_names[0] = core_name; + + init.name = clk_name; + init.ops = &clk_regmap_phase_ops; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = 1; + + x->map = clkc->map; + x->data = phase_data; + x->hw.init = &init; + + ret = devm_clk_hw_register(dev, &x->hw); + if (ret) { + dev_err(dev, "Core %s clock registration failed\n", name); + x = ERR_PTR(ret); + } +err: + kfree(clk_name); + kfree(core_name); + return x; +} + +static int mmc_clkc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mmc_clkc_info *clkc; + struct clk_regmap *mux, *div, *core, *rx, *tx; + struct clk_hw_onecell_data *onecell_data; + + clkc = devm_kzalloc(dev, sizeof(*clkc), GFP_KERNEL); + if (!clkc) + return -ENOMEM; + + clkc->data = (struct mmc_clkc_data *)of_device_get_match_data(dev); + if (!clkc->data) + return -EINVAL; + + clkc->dev = dev; + clkc->map = syscon_node_to_regmap(dev->of_node); + + if (IS_ERR(clkc->map)) { + dev_err(dev, "could not find mmc clock controller\n"); + return PTR_ERR(clkc->map); + } + + onecell_data = devm_kzalloc(dev, sizeof(*onecell_data) + + sizeof(*onecell_data->hws) * MMC_MAX_CLKS, + GFP_KERNEL); + if (!onecell_data) + return -ENOMEM; + + mux = mmc_clkc_register_mux(clkc); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + div = mmc_clkc_register_div(clkc); + if (IS_ERR(div)) + return PTR_ERR(div); + + core = mmc_clkc_register_phase_clk(clkc, "core", "div", + CLK_SET_RATE_PARENT, + &mmc_clkc_core_phase); + if (IS_ERR(core)) + return PTR_ERR(core); + + rx = mmc_clkc_register_phase_clk(clkc, "rx", "core", 0, + &clkc->data->rx); + if (IS_ERR(rx)) + return PTR_ERR(rx); + + tx = mmc_clkc_register_phase_clk(clkc, "tx", "core", 0, + &clkc->data->tx); + if (IS_ERR(tx)) + return PTR_ERR(tx); + + onecell_data->hws[CLKID_MMC_MUX] = &mux->hw, + onecell_data->hws[CLKID_MMC_DIV] = &div->hw, + onecell_data->hws[CLKID_MMC_PHASE_CORE] = &core->hw, + onecell_data->hws[CLKID_MMC_PHASE_RX] = &rx->hw, + onecell_data->hws[CLKID_MMC_PHASE_TX] = &tx->hw, + onecell_data->num = MMC_MAX_CLKS; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + onecell_data); +} + +static struct platform_driver mmc_clkc_driver = { + .probe = mmc_clkc_probe, + .driver = { + .name = "meson-mmc-clkc", + .of_match_table = of_match_ptr(mmc_clkc_match_table), + }, +}; + +module_platform_driver(mmc_clkc_driver);