From patchwork Thu Jul 12 21:12:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yixun Lan X-Patchwork-Id: 10521675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D38456028E for ; Thu, 12 Jul 2018 13:16:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6A6428725 for ; Thu, 12 Jul 2018 13:16:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A7432296E5; Thu, 12 Jul 2018 13:16:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5169D20072 for ; Thu, 12 Jul 2018 13:16:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+HNaUmNkl6ijzRUvfRSIBHjjXPRwGTLh4EexHs1DI60=; b=Q9F0kLOI71LUvE 3uHEXlCyqVdpBRROFya6k+JH0CIq+ULbEIH9KGXpI6V/0yPaZpj91MKEoGY8ws64Dwcdi8JgYxcjZ ztqcfIY4n9KQrdRhFPgTdb/geqtleJ65NZ025xSioyl9epxsbKpFPuZOMAyvi/WXxecQ0w5vsnyGR 8Rl8NOq/W/IN6NXLiwIwRnJ8AIbUXuuA7/RS6TU0zCV5+iP7tyDa70HEQNTurwxJ/q4ZdgGUNT85i 1Sj8UW38ZylJZMmtS7Y/z1rv2FZqgHgwh4jpXrqPSbNcyiKtwo+f57/lvI8+AgDBqlZVmXVAXtIPH B/PYBIwQ5TDA6yN18Ncg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fdbSg-0002Vd-6o; Thu, 12 Jul 2018 13:16:46 +0000 Received: from mail-sh2.amlogic.com ([58.32.228.45]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fdbST-00022K-8f; Thu, 12 Jul 2018 13:16:44 +0000 Received: from localhost.localdomain (10.18.20.250) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 12 Jul 2018 21:15:18 +0800 From: Yixun Lan To: Jerome Brunet , Neil Armstrong Subject: [PATCH v3 1/2] clk: meson: add DT documentation for emmc clock controller Date: Thu, 12 Jul 2018 21:12:43 +0000 Message-ID: <20180712211244.11428-2-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180712211244.11428-1-yixun.lan@amlogic.com> References: <20180712211244.11428-1-yixun.lan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.20.250] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180712_061633_748084_7C73B680 X-CRM114-Status: GOOD ( 10.95 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , devicetree@vger.kernel.org, Stephen Boyd , Kevin Hilman , Michael Turquette , Yixun Lan , linux-kernel@vger.kernel.org, Boris Brezillon , Liang Yang , Qiufang Dai , Miquel Raynal , Carlo Caione , linux-amlogic@lists.infradead.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jian Hu Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Document the MMC sub clock controller driver, the potential consumer of this driver is MMC or NAND. Also add three clock bindings IDs which provided by this driver. Signed-off-by: Yixun Lan Reviewed-by: Rob Herring --- .../bindings/clock/amlogic,mmc-clkc.txt | 31 +++++++++++++++++++ .../clock/amlogic,meson-mmc-clkc.h | 16 ++++++++++ 2 files changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt new file mode 100644 index 000000000000..91018221df1a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt @@ -0,0 +1,31 @@ +* Amlogic MMC Sub Clock Controller Driver + +The Amlogic MMC clock controller generates and supplies clock to support +MMC and NAND controller + +Required Properties: + +- compatible: should be: + "amlogic,meson-gx-mmc-clkc" + "amlogic,meson-axg-mmc-clkc" + +- #clock-cells: should be 1. +- clocks: phandles to clocks corresponding to the clock-names property +- clock-names: list of parent clock names + - "clkin0", "clkin1" + +Parent node should have the following properties : +- compatible: "amlogic,meson-axg-mmc-clkc", "syscon". +- reg: base address and size of the MMC control register space. + +Example: Clock controller node: + +sd_mmc_c_clkc: clock-controller@7000 { + compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; + reg = <0x0 0x7000 0x0 0x4>; + #clock-cells = <1>; + + clock-names = "clkin0", "clkin1"; + clocks = <&clkc CLKID_SD_MMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; +}; diff --git a/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h new file mode 100644 index 000000000000..2ae988ebc3ae --- /dev/null +++ b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson MMC sub clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Yixun Lan + */ + +#ifndef __MMC_CLKC_H +#define __MMC_CLKC_H + +#define CLKID_MMC_DIV 1 +#define CLKID_MMC_PHASE_TX 3 +#define CLKID_MMC_PHASE_RX 4 + +#endif