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[2003:f1:33dd:a400:d12e:ff43:fed1:e981]) by smtp.googlemail.com with ESMTPSA id c7sm5143345wrp.57.2019.06.08.11.06.47 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sat, 08 Jun 2019 11:06:47 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, thierry.reding@gmail.com Subject: [PATCH v2 14/14] pwm: meson: add documentation to the driver Date: Sat, 8 Jun 2019 20:06:26 +0200 Message-Id: <20190608180626.30589-15-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190608180626.30589-1-martin.blumenstingl@googlemail.com> References: <20190608180626.30589-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190608_110650_470788_3076458B X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , Neil Armstrong , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, u.kleine-koenig@pengutronix.de Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a link to the datasheet and a short summary how the hardware works. The goal is to make it easier for other developers to understand why the pwm-meson driver is implemented the way it is. Suggested-by: Uwe Kleine-König Co-authored-by: Neil Armstrong Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong --- drivers/pwm/pwm-meson.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index bb48ba85f756..6a978caba483 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -1,5 +1,23 @@ // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* + * PWM controller driver for Amlogic Meson SoCs. + * + * This PWM is only a set of Gates, Dividers and Counters: + * PWM output is achieved by calculating a clock that permits calculating + * two periods (low and high). The counter then has to be set to switch after + * N cycles for the first half period. + * The hardware has no "polarity" setting. This driver reverses the period + * cycles (the low length is inverted with the high length) for + * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity + * from the hardware. + * Setting the duty cycle will disable and re-enable the PWM output. + * Disabling the PWM stops the output immediately (without waiting for the + * current period to complete first). + * + * The public S922X datasheet contains some documentation for this PWM + * controller starting on page 1084: + * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf + * * Copyright (c) 2016 BayLibre, SAS. * Author: Neil Armstrong * Copyright (C) 2014 Amlogic, Inc.