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Thu, 26 Mar 2020 06:45:22 -0700 (PDT) From: Neil Armstrong To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH v2 09/14] usb: dwc3: meson-g12a: add support for GXL and GXM SoCs Date: Thu, 26 Mar 2020 14:45:01 +0100 Message-Id: <20200326134507.4808-10-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200326134507.4808-1-narmstrong@baylibre.com> References: <20200326134507.4808-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200326_064524_946303_4569FE37 X-CRM114-Status: GOOD ( 13.60 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org In order to add support for the Amlogic GXL/GXM USB Glue, this adds the corresponding : - PHY names - clock names - USB2 PHY init and mode set - regmap setup Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/dwc3-meson-g12a.c | 102 ++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index f3f247d38606..15b8d9d4accd 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -101,6 +101,11 @@ #define PHY_COUNT 3 #define USB2_OTG_PHY 1 +static struct clk_bulk_data meson_gxl_clocks[] = { + { .id = "usb_ctrl" }, + { .id = "ddr" }, +}; + static struct clk_bulk_data meson_g12a_clocks[] = { { .id = NULL }, }; @@ -111,6 +116,10 @@ static struct clk_bulk_data meson_a1_clocks[] = { { .id = "xtal_usb_ctrl" }, }; +static const char *meson_gxm_phy_names[] = { + "usb2-phy0", "usb2-phy1", "usb2-phy2", +}; + static const char *meson_g12a_phy_names[] = { "usb2-phy0", "usb2-phy1", "usb3-phy0", }; @@ -145,16 +154,53 @@ struct dwc3_meson_g12a_drvdata { int (*usb_post_init)(struct dwc3_meson_g12a *priv); }; +static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base); static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base); static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, - enum phy_mode mode); + enum phy_mode mode); +static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode); static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode); +static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode); static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv); +static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv); + +static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv); + +static struct dwc3_meson_g12a_drvdata gxl_drvdata = { + .otg_switch_supported = true, + .otg_phy_host_port_disable = true, + .clks = meson_gxl_clocks, + .num_clks = ARRAY_SIZE(meson_g12a_clocks), + .phy_names = meson_a1_phy_names, + .num_phys = ARRAY_SIZE(meson_a1_phy_names), + .setup_regmaps = dwc3_meson_gxl_setup_regmaps, + .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy, + .set_phy_mode = dwc3_meson_gxl_set_phy_mode, + .usb_init = dwc3_meson_gxl_usb_init, + .usb_post_init = dwc3_meson_gxl_usb_post_init, +}; + +static struct dwc3_meson_g12a_drvdata gxm_drvdata = { + .otg_switch_supported = true, + .otg_phy_host_port_disable = true, + .clks = meson_gxl_clocks, + .num_clks = ARRAY_SIZE(meson_g12a_clocks), + .phy_names = meson_gxm_phy_names, + .num_phys = ARRAY_SIZE(meson_gxm_phy_names), + .setup_regmaps = dwc3_meson_gxl_setup_regmaps, + .usb2_init_phy = dwc3_meson_gxl_usb2_init_phy, + .set_phy_mode = dwc3_meson_gxl_set_phy_mode, + .usb_init = dwc3_meson_gxl_usb_init, + .usb_post_init = dwc3_meson_gxl_usb_post_init, +}; /* * For GXL and GXM SoCs: @@ -209,6 +255,21 @@ struct dwc3_meson_g12a { const struct dwc3_meson_g12a_drvdata *drvdata; }; +static int dwc3_meson_gxl_set_phy_mode(struct dwc3_meson_g12a *priv, + int i, enum phy_mode mode) +{ + return phy_set_mode(priv->phys[i], mode); +} + +static int dwc3_meson_gxl_usb2_init_phy(struct dwc3_meson_g12a *priv, int i, + enum phy_mode mode) +{ + /* On GXL PHY must be started in device mode for DWC2 init */ + return priv->drvdata->set_phy_mode(priv, i, + (i == USB2_OTG_PHY) ? PHY_MODE_USB_DEVICE + : PHY_MODE_USB_HOST); +} + static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { @@ -556,6 +617,18 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, return 0; } +static int dwc3_meson_gxl_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base) +{ + /* GXL controls the PHY mode in the PHY registers unlike G12A */ + priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev, base, + &phy_meson_g12a_usb_glue_regmap_conf); + if (IS_ERR(priv->usb_glue_regmap)) + return PTR_ERR(priv->usb_glue_regmap); + + return 0; +} + static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, void __iomem *base) { @@ -596,6 +669,25 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) return dwc3_meson_g12a_usb_init_glue(priv, priv->otg_phy_mode); } +static int dwc3_meson_gxl_usb_init(struct dwc3_meson_g12a *priv) +{ + return dwc3_meson_g12a_usb_init_glue(priv, PHY_MODE_USB_DEVICE); +} + +static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv) +{ + int ret; + + ret = priv->drvdata->set_phy_mode(priv, USB2_OTG_PHY, + priv->otg_phy_mode); + if (ret) + return ret; + + dwc3_meson_g12a_usb_otg_apply_mode(priv, priv->otg_phy_mode); + + return 0; +} + static int dwc3_meson_g12a_probe(struct platform_device *pdev) { struct dwc3_meson_g12a *priv; @@ -825,6 +917,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = { }; static const struct of_device_id dwc3_meson_g12a_match[] = { + { + .compatible = "amlogic,meson-gxl-usb-ctrl", + .data = &gxl_drvdata, + }, + { + .compatible = "amlogic,meson-gxm-usb-ctrl", + .data = &gxm_drvdata, + }, { .compatible = "amlogic,meson-g12a-usb-ctrl", .data = &g12a_drvdata,