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Fri, 03 Jul 2020 01:07:44 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, dri-devel@lists.freedesktop.org Subject: [PATCH v9 5/6] drm/meson: overlay: setup overlay for Amlogic FBC Scatter Memory layout Date: Fri, 3 Jul 2020 10:07:27 +0200 Message-Id: <20200703080728.25207-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200703080728.25207-1-narmstrong@baylibre.com> References: <20200703080728.25207-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200703_040746_351936_C372E0F8 X-CRM114-Status: GOOD ( 12.82 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jianxin.pan@amlogic.com, Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org Setup the Amlogic FBC decoder for the VD1 video overlay plane to use read the FBC header as Scatter Memory layout reference. Tested-by: Kevin Hilman Signed-off-by: Neil Armstrong Reviewed-by: Kevin Hilman --- drivers/gpu/drm/meson/meson_overlay.c | 53 ++++++++++++++++++--------- 1 file changed, 35 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c index 1566a887d482..1f7b2055e012 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -490,6 +490,10 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, AMLOGIC_FBC_OPTION_MEM_SAVING)) priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE; + if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) == + AMLOGIC_FBC_LAYOUT_SCATTER) + priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE; + priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE; priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256); @@ -675,23 +679,32 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, } if (priv->viu.vd1_afbc) { - /* Default mode is 4k per superblock */ - unsigned long block_size = 4096; - unsigned long body_size; - - /* 8bit mem saving mode is 3072bytes per superblock */ - if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) - block_size = 3072; - - body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * - (ALIGN(priv->viu.vd1_height0, 32) / 32) * - block_size; - - priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; - - /* Header is after body content */ - priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + - body_size) >> 4; + if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) { + /* + * In Scatter mode, the header contains the physical + * body content layout, thus the body content + * size isn't needed. + */ + priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4; + priv->viu.vd1_afbc_body_addr = 0; + } else { + /* Default mode is 4k per superblock */ + unsigned long block_size = 4096; + unsigned long body_size; + + /* 8bit mem saving mode is 3072bytes per superblock */ + if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE) + block_size = 3072; + + body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) * + (ALIGN(priv->viu.vd1_height0, 32) / 32) * + block_size; + + priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4; + /* Header is after body content */ + priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 + + body_size) >> 4; + } } priv->viu.vd1_enabled = true; @@ -754,7 +767,8 @@ static bool meson_overlay_format_mod_supported(struct drm_plane *plane, return false; } - if (layout != AMLOGIC_FBC_LAYOUT_BASIC) { + if (layout != AMLOGIC_FBC_LAYOUT_BASIC && + layout != AMLOGIC_FBC_LAYOUT_SCATTER) { DRM_DEBUG_KMS("%llx invalid layout %x\n", modifier, layout); return false; @@ -800,8 +814,11 @@ static const uint32_t supported_drm_formats[] = { }; static const uint64_t format_modifiers[] = { + DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, + AMLOGIC_FBC_OPTION_MEM_SAVING), DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, AMLOGIC_FBC_OPTION_MEM_SAVING), + DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0), DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0), DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID,