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[2003:f1:372a:4000:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id f20sm26576696edx.92.2020.12.29.17.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 17:27:42 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH 2/5] dt-bindings: Amlogic: add the documentation for the SECBUS2 registers Date: Wed, 30 Dec 2020 02:27:21 +0100 Message-Id: <20201230012724.1326156-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> References: <20201230012724.1326156-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201229_202744_084965_CEA9244B X-CRM114-Status: GOOD ( 14.25 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ohad@wizery.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which contains registers for various IP blocks such as pin-controller bits for the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. The registers can be accessed directly when not running in "secure mode". When "secure mode" is enabled then these registers have to be accessed through secure monitor calls. So far these SoCs are always known to boot in "non-secure mode". Add a binding documentation using syscon (as these registers are shared across different IPs) for the SECBUS2 registers. Signed-off-by: Martin Blumenstingl --- .../arm/amlogic/amlogic,meson-mx-secbus2.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml new file mode 100644 index 000000000000..cfa8e9de6c28 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface + +maintainers: + - Martin Blumenstingl + +description: | + The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which + contains registers for various IP blocks such as pin-controller bits for + the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. + The registers can be accessed directly when not running in "secure mode". + When "secure mode" is enabled then these registers have to be accessed + through secure monitor calls. + +# We need a select here so we don't match all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - amlogic,meson8-secbus2 + - amlogic,meson8b-secbus2 + required: + - compatible + +properties: + compatible: + items: + - enum: + - amlogic,meson8-secbus2 + - amlogic,meson8b-secbus2 + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + secbus2: system-controller@4000 { + compatible = "amlogic,meson8-secbus2", "syscon"; + reg = <0x4000 0x2000>; + };