@@ -535,7 +535,7 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
/*
* Assume that if it has already been selected (for example by the
- * bootloader), enough time has aready passed.
+ * bootloader), enough time has already passed.
*/
if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
osc->prepared = true;
@@ -2,7 +2,7 @@
/*
* ARTPEC-6 clock initialization
*
- * Copyright 2015-2016 Axis Comunications AB.
+ * Copyright 2015-2016 Axis Communications AB.
*/
#include <linux/clk-provider.h>
@@ -89,7 +89,7 @@
* Parameters for VCO frequency configuration
*
* VCO frequency =
- * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
+ * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv)
*/
struct iproc_pll_vco_param {
unsigned long rate;
@@ -510,7 +510,7 @@ static bool kona_clk_valid(struct kona_clk *bcm_clk)
* placeholders for non-supported clocks. Keep track of the
* position of each clock name in the original array.
*
- * Allocates an array of pointers to to hold the names of all
+ * Allocates an array of pointers to hold the names of all
* non-null entries in the original array, and returns a pointer to
* that array in *names. This will be used for registering the
* clock with the common clock code. On successful return,
@@ -34,7 +34,7 @@
* and assume that the IP, that needs m and n, has also its own
* prescaler, which is capable to divide by 2^scale. In this way
* we get the denominator to satisfy the desired range (2) and
- * at the same time much much better result of m and n than simple
+ * at the same time a much better result of m and n than simple
* saturated values.
*/
@@ -655,7 +655,7 @@ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
f = synth->data->freq_vco;
f *= n_den >> 4;
- /* Now we need to to 64-bit division: f/n_num */
+ /* Now we need to do 64-bit division: f/n_num */
/* And compensate for the 4 bits we dropped */
f = div64_u64(f, (n_num >> 4));
@@ -2232,7 +2232,7 @@ static struct clk_regmap meson8b_vpu_1 = {
};
/*
- * The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
+ * The VPU clock has two identical clock trees (vpu_0 and vpu_1)
* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
* actually manage this glitch-free mux because it does top-to-bottom
* updates the each clock tree and switches to the "inactive" one when
@@ -76,7 +76,7 @@ static int mmp_pm_domain_power_off(struct generic_pm_domain *genpd)
if (pm_domain->lock)
spin_lock_irqsave(pm_domain->lock, flags);
- /* Turn off and isolate the the power island. */
+ /* Turn off and isolate the power island. */
val = readl(pm_domain->reg);
val &= ~pm_domain->power_on;
val &= ~0x100;
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017, Intel Corporation
*/