From patchwork Wed Sep 7 08:04:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 12968593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5420C38145 for ; Wed, 7 Sep 2022 08:14:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=baxGMCtEo8jwX2eMP/45nXH74MFcvZAbsP5TEpta+fc=; b=w6HxJroA9+1hkt E1z16w/+hszjCQU+wT0sff38VPBXVwaupXvR68TOZ9yxi9z2xtn1SAR7ZB0aQPFuaMbA3FRJG4X1Z HLp1Mmp5VshNe3JRwn3ZyXPhSqJ0p3li4VVNKb541RxVMNq7wdd3f3IXt//kmkQtR+FXhJFj6/rmr sV2Fmh/p1l3cDWSZfB9kICLqKhlQ1ztL7WATqca5msX7h8yEB9I8sSuE3n6EbWuTmm0bBicitReYx WstXHYykMphjB9ZID+t5ysiL4qiMFNzX5Sh1Ds9vSZpzRxlmcfPTS63SVQ4rUxth7pS5IyNF/uKWw +O9No5p8SlJtngTjZx5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oVqCZ-00472d-Ms; Wed, 07 Sep 2022 08:14:27 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oVq2g-0040gb-TL; Wed, 07 Sep 2022 08:04:16 +0000 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 7 Sep 2022 16:04:10 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v9 1/5] dt-bindings: nand: meson: fix meson nfc clock Date: Wed, 7 Sep 2022 16:04:01 +0800 Message-ID: <20220907080405.28240-2-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220907080405.28240-1-liang.yang@amlogic.com> References: <20220907080405.28240-1-liang.yang@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_010414_986454_5DE1C12F X-CRM114-Status: GOOD ( 11.21 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted and the current binding was never valid. the reasons for giving up are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link fot more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Acked-by: Rob Herring Signed-off-by: Liang Yang --- .../bindings/mtd/amlogic,meson-nand.txt | 29 ++++++++----------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt index 5794ab1147c1..5d5cdfef417f 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -7,18 +7,19 @@ Required properties: - compatible : contains one of: - "amlogic,meson-gxl-nfc" - "amlogic,meson-axg-nfc" + +- reg : Offset and length of the register set + +- reg-names : "nfc" is the register set for NFC controller and "emmc" + is the register set for MCI controller. + - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. - clock-names: Should contain the following: "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C + "device" - parent clock for internal NFC Optional children nodes: Children nodes represent the available nand chips. @@ -28,24 +29,18 @@ see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindi Example demonstrate on AXG SoC: - sd_emmc_c_clkc: mmc@7000 { - compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; - reg = <0x0 0x7000 0x0 0x800>; - }; - nand-controller@7800 { compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>; + reg = <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names = "nfc", "emmc"; #address-cells = <1>; #size-cells = <0>; interrupts = ; clocks = <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names = "core", "device", "rx", "tx"; - amlogic,mmc-syscon = <&sd_emmc_c_clkc>; + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; pinctrl-names = "default"; pinctrl-0 = <&nand_pins>;