| Message ID | 20221125111921.37261-4-tomeu.vizoso@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support for the NPU in Vim3 | expand |
On 25/11/2022 12:19, Tomeu Vizoso wrote: > Based on power initialization sequence in downstream driver. > > Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> > --- > drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c > index dd5f2a13ceb5..925cfaf50d11 100644 > --- a/drivers/soc/amlogic/meson-ee-pwrc.c > +++ b/drivers/soc/amlogic/meson-ee-pwrc.c > @@ -46,6 +46,9 @@ > #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) > #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) > > +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) > +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) > + > struct meson_ee_pwrc; > struct meson_ee_pwrc_domain; > > @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); > static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); > static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); > > +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \ > + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ > + .sleep_mask = BIT(16) | BIT(17), \ > + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ > + .iso_mask = BIT(16) | BIT(17), \ > + }; > + > /* Memory PD Domains */ > > #define VPU_MEMPD(__reg) \ > @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { > { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, > }; > > +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { > + { G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff }, > + { G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff }, Weird it's not 0xff like on SM1, I looked at the A311D Datasheet and HHI_NANOQ_MEM_PD_REG0 is 31:0 so 0xffffffff is correct, but HHI_NANOQ_MEM_PD_REG1 is 23:0 so 0xFFFFFF is the correct value. Bur please replace with GENMASK(31, 0) and GENMASK(23, 0) to align with the rest of the code. > +}; > + > #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ > { \ > .name = __name, \ > @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { > [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, > pwrc_ee_is_powered_off, 11, 2), > [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), > + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, > + pwrc_ee_is_powered_off), > }; > > static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { With this fixed: Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Thanks, Neil
diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index dd5f2a13ceb5..925cfaf50d11 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -46,6 +46,9 @@ #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) + struct meson_ee_pwrc; struct meson_ee_pwrc_domain; @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \ + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ + .sleep_mask = BIT(16) | BIT(17), \ + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ + .iso_mask = BIT(16) | BIT(17), \ + }; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { + { G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff }, + { G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, pwrc_ee_is_powered_off, 11, 2), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
Based on power initialization sequence in downstream driver. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)