diff mbox series

drm/meson: fix 1px pink line on GXM when scaling video overlay

Message ID 20230303120626.3281-1-christianshewitt@gmail.com (mailing list archive)
State Superseded
Delegated to: Neil Armstrong
Headers show
Series drm/meson: fix 1px pink line on GXM when scaling video overlay | expand

Commit Message

Christian Hewitt March 3, 2023, 12:06 p.m. UTC
Playing media with a resolution smaller than the crtc size requires the
video overlay to be scaled for output and GXM boards display a 1px pink
line on the bottom of the scaled overlay. Comparing registers with the
downstream vendor driver revealed some differences:

- The vendor driver sets BIT(17) | BIT(13) for VPP_DOLBY_CTRL
- The vendor driver sets VPP_DUMMY_DATA

Setting those values prevents the 1px pink line from being seen.

Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
Suggested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/gpu/drm/meson/meson_registers.h | 2 +-
 drivers/gpu/drm/meson/meson_vpp.c       | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 0f3cafab8860..e4af333fd839 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -534,7 +534,7 @@ 
 #define VPP_PEAKING_VGAIN 0x1d92
 #define VPP_PEAKING_NLP_1 0x1d93
 #define VPP_DOLBY_CTRL 0x1d93
-#define VPP_PPS_DUMMY_DATA_MODE (1 << 17)
+#define VPP_PPS_DUMMY_DATA_MODE (1 << 17 | 1 << 13)
 #define VPP_PEAKING_NLP_2 0x1d94
 #define VPP_PEAKING_NLP_3 0x1d95
 #define VPP_PEAKING_NLP_4 0x1d96
diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c
index 154837688ab0..5df1957c8e41 100644
--- a/drivers/gpu/drm/meson/meson_vpp.c
+++ b/drivers/gpu/drm/meson/meson_vpp.c
@@ -100,6 +100,8 @@  void meson_vpp_init(struct meson_drm *priv)
 			       priv->io_base + _REG(VPP_DOLBY_CTRL));
 		writel_relaxed(0x1020080,
 				priv->io_base + _REG(VPP_DUMMY_DATA1));
+		writel_relaxed(0x42020,
+				priv->io_base + _REG(VPP_DUMMY_DATA));
 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 		writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));