| Message ID | 20230528140001.1057084-2-adrian.larumbe@collabora.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add additional YUV420 bus format check for dw-meson's bridge enable | expand |
On 28/05/2023 15:59, Adrián Larumbe wrote: > Right now clocking value selection code is prioritising RGB, YUV444 modes > over YUV420 for HDMI2 sinks. However, because of the bus format selection > procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always > be picked during the drm bridge chain check stage. > > Later on dw_hdmi_setup will configure a colour space based on the bus > format that doesn't match the pixel value we had calculated as described > above. > > Fix it by bringing back dw-hdmi bus format check when picking the right > pixel clock. > > Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> > --- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++++ > drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ++-- > include/drm/bridge/dw_hdmi.h | 2 ++ > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > index 603bb3c51027..d59a547f9cb2 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > @@ -3346,6 +3346,12 @@ static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) > return 0; > } > > +bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) > +{ > + return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format); > +} > +EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); > + > struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, > const struct dw_hdmi_plat_data *plat_data) > { > diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c > index 3d046878ce6c..b49bb0d86efe 100644 > --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c > +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c > @@ -379,8 +379,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, > mode->clock > 340000 ? 40 : 10); > > if (drm_mode_is_420_only(display, mode) || > - (!is_hdmi2_sink && > - drm_mode_is_420_also(display, mode))) > + (!is_hdmi2_sink && drm_mode_is_420_also(display, mode)) || > + dw_hdmi_bus_fmt_is_420(hdmi)) > mode_is_420 = true; > > /* Enable clocks */ > diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h > index f668e75fbabe..6a46baa0737c 100644 > --- a/include/drm/bridge/dw_hdmi.h > +++ b/include/drm/bridge/dw_hdmi.h > @@ -206,4 +206,6 @@ void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, > bool force, bool disabled, bool rxsense); > void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); > > +bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); > + > #endif /* __IMX_HDMI_H__ */ Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 603bb3c51027..d59a547f9cb2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3346,6 +3346,12 @@ static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) return 0; } +bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) +{ + return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format); +} +EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); + struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data) { diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 3d046878ce6c..b49bb0d86efe 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -379,8 +379,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, mode->clock > 340000 ? 40 : 10); if (drm_mode_is_420_only(display, mode) || - (!is_hdmi2_sink && - drm_mode_is_420_also(display, mode))) + (!is_hdmi2_sink && drm_mode_is_420_also(display, mode)) || + dw_hdmi_bus_fmt_is_420(hdmi)) mode_is_420 = true; /* Enable clocks */ diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index f668e75fbabe..6a46baa0737c 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -206,4 +206,6 @@ void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense); void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); +bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); + #endif /* __IMX_HDMI_H__ */
Right now clocking value selection code is prioritising RGB, YUV444 modes over YUV420 for HDMI2 sinks. However, because of the bus format selection procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always be picked during the drm bridge chain check stage. Later on dw_hdmi_setup will configure a colour space based on the bus format that doesn't match the pixel value we had calculated as described above. Fix it by bringing back dw-hdmi bus format check when picking the right pixel clock. Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++++ drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ++-- include/drm/bridge/dw_hdmi.h | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-)