| Message ID | 20231109054037.3864802-1-avkrasnov@salutedevices.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] mtd: rawnand: meson: initialize clock register | expand |
On 09.11.2023 08:40, Arseniy Krasnov wrote: > Clock register must be also initialized during controller probing. If > this is not performed (for example by bootloader before) - controller > will not work. > > Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> > --- > drivers/mtd/nand/raw/meson_nand.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c > index 0d4d358152d7..4e7fa943928c 100644 > --- a/drivers/mtd/nand/raw/meson_nand.c > +++ b/drivers/mtd/nand/raw/meson_nand.c > @@ -91,6 +91,8 @@ > > /* eMMC clock register, misc control */ > #define CLK_SELECT_NAND BIT(31) > +#define CLK_ALWAYS_ON_NAND BIT(24) > +#define CLK_ENABLE_VALUE 0x245 ^^^^^^ Hi, @Liang, it will be great, if You'll give some details about this magic value. I get it from vendor's driver and it makes NAND controller alive, but I don't have any docs. Thanks, Arseniy > > #define NFC_CLK_CYCLE 6 > > @@ -1152,7 +1154,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) > return PTR_ERR(nfc->nand_clk); > > /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ > - writel(CLK_SELECT_NAND | readl(nfc->reg_clk), > + writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_ENABLE_VALUE, > nfc->reg_clk); > > ret = clk_prepare_enable(nfc->core_clk);
Hi Arseniy, I remember that you asked it in another email, but i forgot to reply. Sorry On 2023/11/12 18:08, Arseniy Krasnov wrote: > [ EXTERNAL EMAIL ] > > On 09.11.2023 08:40, Arseniy Krasnov wrote: >> Clock register must be also initialized during controller probing. If >> this is not performed (for example by bootloader before) - controller >> will not work. >> >> Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> >> --- >> drivers/mtd/nand/raw/meson_nand.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c >> index 0d4d358152d7..4e7fa943928c 100644 >> --- a/drivers/mtd/nand/raw/meson_nand.c >> +++ b/drivers/mtd/nand/raw/meson_nand.c >> @@ -91,6 +91,8 @@ >> >> /* eMMC clock register, misc control */ >> #define CLK_SELECT_NAND BIT(31) >> +#define CLK_ALWAYS_ON_NAND BIT(24) >> +#define CLK_ENABLE_VALUE 0x245 > ^^^^^^ > > Hi, > > @Liang, it will be great, if You'll give some details about this magic value. I get it > from vendor's driver and it makes NAND controller alive, but I don't have any docs. Bit 7:6 is used to select the clock source for NAND controller. 00 : more clock source 01 : fix pll is select, commonly 1GHZ in Amlogic soc chips. The implementation in meson nfc driver should select '01', so you could do like this : #define CLK_SELECT_FIX_PLL2 BIT(6) writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_SELECT_FIX_PLL2, nfc->reg_clk); Bit 5:0 is the clock divider. > > Thanks, Arseniy > >> >> #define NFC_CLK_CYCLE 6 >> >> @@ -1152,7 +1154,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) >> return PTR_ERR(nfc->nand_clk); >> >> /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ >> - writel(CLK_SELECT_NAND | readl(nfc->reg_clk), >> + writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_ENABLE_VALUE, >> nfc->reg_clk); >> >> ret = clk_prepare_enable(nfc->core_clk);
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index 0d4d358152d7..4e7fa943928c 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -91,6 +91,8 @@ /* eMMC clock register, misc control */ #define CLK_SELECT_NAND BIT(31) +#define CLK_ALWAYS_ON_NAND BIT(24) +#define CLK_ENABLE_VALUE 0x245 #define NFC_CLK_CYCLE 6 @@ -1152,7 +1154,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) return PTR_ERR(nfc->nand_clk); /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - writel(CLK_SELECT_NAND | readl(nfc->reg_clk), + writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_ENABLE_VALUE, nfc->reg_clk); ret = clk_prepare_enable(nfc->core_clk);
Clock register must be also initialized during controller probing. If this is not performed (for example by bootloader before) - controller will not work. Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> --- drivers/mtd/nand/raw/meson_nand.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)