| Message ID | 20240515185103.20256-3-ddrokosov@salutedevices.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver | expand |
On Wed, 15 May 2024 21:47:25 +0300, Dmitry Rokosov wrote: > The 'syspll' PLL is a general-purpose PLL designed specifically for the > CPU clock. It is capable of producing output frequencies within the > range of 768MHz to 1536MHz. > > The 'syspll_in' source clock is an optional parent connection from the > peripherals clock controller. > > Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> > --- > .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 9 +++++++-- > include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 1 + > 2 files changed, 8 insertions(+), 2 deletions(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml index a59b188a8bf5..c99274d2a9bd 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -26,11 +26,15 @@ properties: items: - description: input fixpll_in - description: input hifipll_in + - description: input syspll_in + minItems: 2 # syspll_in is optional clock-names: items: - const: fixpll_in - const: hifipll_in + - const: syspll_in + minItems: 2 # syspll_in is optional required: - compatible @@ -53,7 +57,8 @@ examples: reg = <0 0x7c80 0 0x18c>; #clock-cells = <1>; clocks = <&clkc_periphs CLKID_FIXPLL_IN>, - <&clkc_periphs CLKID_HIFIPLL_IN>; - clock-names = "fixpll_in", "hifipll_in"; + <&clkc_periphs CLKID_HIFIPLL_IN>, + <&clkc_periphs CLKID_SYSPLL_IN>; + clock-names = "fixpll_in", "hifipll_in", "syspll_in"; }; }; diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 2b660c0f2c9f..0dfc5e78a2d5 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -21,5 +21,6 @@ #define CLKID_FCLK_DIV5 8 #define CLKID_FCLK_DIV7 9 #define CLKID_HIFI_PLL 10 +#define CLKID_SYS_PLL 11 #endif /* __A1_PLL_CLKC_H */
The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> --- .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 9 +++++++-- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-)