From patchwork Tue Jul 30 12:50:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 13747376 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36D59C3DA7F for ; Tue, 30 Jul 2024 12:51:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Drop these poke and let CCF handle this using DT assigned-clocks. HHI is a collection of Amlogic devices, such as clocks, reset, power domains and phys. This is another step to get rid of HHI access in Amlogic display drivers and possibly stop using the component API. Signed-off-by: Jerome Brunet --- This change depends on: * 0602ba0dcd0e ("arm64: dts: amlogic: gx: correct hdmi clocks") * 1443b6ea806d ("arm64: dts: amlogic: setup hdmi system clock") Time is needed for these changes to sink in u-boot and distros, making this change safe to apply. drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 6c18d97b8b16..b54c1e3093e9 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -111,7 +111,6 @@ #define HDMITX_TOP_G12A_OFFSET 0x8000 /* HHI Registers */ -#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */ #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */ #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */ #define PHY_CNTL1_INIT 0x03900000 @@ -419,9 +418,6 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi) { struct meson_drm *priv = meson_dw_hdmi->priv; - /* Enable clocks */ - regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); - /* Bring out of reset */ regmap_write(meson_dw_hdmi->top, HDMITX_TOP_SW_RESET, 0); msleep(20);