diff mbox series

[2/2] clk: meson: axg-audio: fix sm1 mclk_pad support

Message ID 20240906131802.630513-2-theo.debrouwere@faytech.de (mailing list archive)
State New
Delegated to: Neil Armstrong
Headers show
Series [1/2] dt-bindings: clk: axg-audio: add missing sm1 pad bindings | expand

Commit Message

Theo Debrouwere Sept. 6, 2024, 1:18 p.m. UTC 
Fix the mclk_pad_0/1 of the sm1 family.
The pads have an additional divider & gate.

Signed-off-by: Theo Debrouwere <theo.debrouwere@faytech.de>
---
 drivers/clk/meson/axg-audio.c | 36 +++++++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index e03a5bf899c0..838281218e71 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -323,6 +323,16 @@  static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
 	AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,		\
 		CLK_SET_RATE_NO_REPARENT)
 
+#define AUD_TDM_PAD_MUX(_name, _reg, _shift, _parents)			\
+	AUD_MUX(_name##_sel, _reg, 0x7, _shift, 0, _parents,		\
+		CLK_SET_RATE_NO_REPARENT)
+#define AUD_TDM_PAD_DIV(_name, _reg, _shift)				\
+	AUD_DIV(_name##_div, _reg, _shift, 8, CLK_DIVIDER_ROUND_CLOSEST,\
+		aud_##_name##_sel, CLK_SET_RATE_PARENT)
+#define AUD_TDM_PAD_GATE(_name, _reg, _bit)				\
+	AUD_GATE(_name, _reg, _bit, aud_##_name##_div,			\
+		 CLK_SET_RATE_PARENT)
+
 /* Common Clocks */
 static struct clk_regmap ddr_arb =
 	AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
@@ -793,10 +803,20 @@  static struct clk_regmap sm1_mst_e_mclk =
 static struct clk_regmap sm1_mst_f_mclk =
 	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
 
-static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
-	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
-static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
-	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_mclk_pad_0_sel = AUD_TDM_PAD_MUX(
+	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 8, mclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_mclk_pad_0_div = AUD_TDM_PAD_DIV(
+	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0);
+static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_GATE(
+	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 15);
+
+static struct clk_regmap sm1_tdm_mclk_pad_1_sel = AUD_TDM_PAD_MUX(
+	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 24, mclk_pad_ctrl_parent_data);
+static struct clk_regmap sm1_tdm_mclk_pad_1_div = AUD_TDM_PAD_DIV(
+	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 16);
+static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_GATE(
+	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 31);
+
 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
 	tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
@@ -1232,6 +1252,10 @@  static struct clk_hw *sm1_audio_hw_clks[] = {
 	[AUD_CLKID_SYSCLK_A_EN]		= &sm1_sysclk_a_en.hw,
 	[AUD_CLKID_SYSCLK_B_DIV]	= &sm1_sysclk_b_div.hw,
 	[AUD_CLKID_SYSCLK_B_EN]		= &sm1_sysclk_b_en.hw,
+	[AUD_CLKID_TDM_MCLK_PAD0_SEL]	= &sm1_tdm_mclk_pad_0_sel.hw,
+	[AUD_CLKID_TDM_MCLK_PAD0_DIV]	= &sm1_tdm_mclk_pad_0_div.hw,
+	[AUD_CLKID_TDM_MCLK_PAD1_SEL]	= &sm1_tdm_mclk_pad_1_sel.hw,
+	[AUD_CLKID_TDM_MCLK_PAD1_DIV]	= &sm1_tdm_mclk_pad_1_div.hw,
 };
 
 
@@ -1646,6 +1670,10 @@  static struct clk_regmap *const sm1_clk_regmaps[] = {
 	&sm1_sysclk_a_en,
 	&sm1_sysclk_b_div,
 	&sm1_sysclk_b_en,
+	&sm1_tdm_mclk_pad_0_sel,
+	&sm1_tdm_mclk_pad_0_div,
+	&sm1_tdm_mclk_pad_1_sel,
+	&sm1_tdm_mclk_pad_1_div,
 };
 
 struct axg_audio_reset_data {