| Message ID | 20240913121152.817575-4-jan.dakinevich@salutedevices.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add A1 Soc audio clock controller driver | expand |
On Fri, Sep 13, 2024 at 03:11:50PM +0300, Jan Dakinevich wrote: > Add device tree bindings for A1 SoC audio clock and reset controllers. > > Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
On Fri 13 Sep 2024 at 15:11, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote: > Add device tree bindings for A1 SoC audio clock and reset controllers. > > Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> Reset and clock are now independent. Please split the patch and send the changes in the related series, bindings before the driver change. > --- > .../clock/amlogic,axg-audio-clkc.yaml | 3 + > .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ > .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ > 3 files changed, 154 insertions(+) > create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h > create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > index fd7982dd4cea..df9eb8ce28dc 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > @@ -18,6 +18,8 @@ description: > properties: > compatible: > enum: > + - amlogic,a1-audio-clkc > + - amlogic,a1-audio-vad-clkc > - amlogic,axg-audio-clkc > - amlogic,g12a-audio-clkc > - amlogic,sm1-audio-clkc > @@ -114,6 +116,7 @@ allOf: > compatible: > contains: > enum: > + - amlogic,a1-audio-clkc > - amlogic,g12a-audio-clkc > - amlogic,sm1-audio-clkc > then: > diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h > new file mode 100644 > index 000000000000..6534d1878816 > --- /dev/null > +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h > @@ -0,0 +1,122 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. > + * > + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> > + */ > + > +#ifndef __A1_AUDIO_CLKC_BINDINGS_H > +#define __A1_AUDIO_CLKC_BINDINGS_H > + > +#define AUD_CLKID_DDR_ARB 1 > +#define AUD_CLKID_TDMIN_A 2 > +#define AUD_CLKID_TDMIN_B 3 > +#define AUD_CLKID_TDMIN_LB 4 > +#define AUD_CLKID_LOOPBACK 5 > +#define AUD_CLKID_TDMOUT_A 6 > +#define AUD_CLKID_TDMOUT_B 7 > +#define AUD_CLKID_FRDDR_A 8 > +#define AUD_CLKID_FRDDR_B 9 > +#define AUD_CLKID_TODDR_A 10 > +#define AUD_CLKID_TODDR_B 11 > +#define AUD_CLKID_SPDIFIN 12 > +#define AUD_CLKID_RESAMPLE 13 > +#define AUD_CLKID_EQDRC 14 > +#define AUD_CLKID_LOCKER 15 > +#define AUD_CLKID_MST_A_MCLK_SEL 16 > +#define AUD_CLKID_MST_A_MCLK_DIV 17 > +#define AUD_CLKID_MST_A_MCLK 18 > +#define AUD_CLKID_MST_B_MCLK_SEL 19 > +#define AUD_CLKID_MST_B_MCLK_DIV 20 > +#define AUD_CLKID_MST_B_MCLK 21 > +#define AUD_CLKID_MST_C_MCLK_SEL 22 > +#define AUD_CLKID_MST_C_MCLK_DIV 23 > +#define AUD_CLKID_MST_C_MCLK 24 > +#define AUD_CLKID_MST_D_MCLK_SEL 25 > +#define AUD_CLKID_MST_D_MCLK_DIV 26 > +#define AUD_CLKID_MST_D_MCLK 27 > +#define AUD_CLKID_SPDIFIN_CLK_SEL 28 > +#define AUD_CLKID_SPDIFIN_CLK_DIV 29 > +#define AUD_CLKID_SPDIFIN_CLK 30 > +#define AUD_CLKID_RESAMPLE_CLK_SEL 31 > +#define AUD_CLKID_RESAMPLE_CLK_DIV 32 > +#define AUD_CLKID_RESAMPLE_CLK 33 > +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34 > +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35 > +#define AUD_CLKID_LOCKER_IN_CLK 36 > +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37 > +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38 > +#define AUD_CLKID_LOCKER_OUT_CLK 39 > +#define AUD_CLKID_EQDRC_CLK_SEL 40 > +#define AUD_CLKID_EQDRC_CLK_DIV 41 > +#define AUD_CLKID_EQDRC_CLK 42 > +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43 > +#define AUD_CLKID_MST_A_SCLK_DIV 44 > +#define AUD_CLKID_MST_A_SCLK_POST_EN 45 > +#define AUD_CLKID_MST_A_SCLK 46 > +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47 > +#define AUD_CLKID_MST_B_SCLK_DIV 48 > +#define AUD_CLKID_MST_B_SCLK_POST_EN 49 > +#define AUD_CLKID_MST_B_SCLK 50 > +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51 > +#define AUD_CLKID_MST_C_SCLK_DIV 52 > +#define AUD_CLKID_MST_C_SCLK_POST_EN 53 > +#define AUD_CLKID_MST_C_SCLK 54 > +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55 > +#define AUD_CLKID_MST_D_SCLK_DIV 56 > +#define AUD_CLKID_MST_D_SCLK_POST_EN 57 > +#define AUD_CLKID_MST_D_SCLK 58 > +#define AUD_CLKID_MST_A_LRCLK_DIV 59 > +#define AUD_CLKID_MST_A_LRCLK 60 > +#define AUD_CLKID_MST_B_LRCLK_DIV 61 > +#define AUD_CLKID_MST_B_LRCLK 62 > +#define AUD_CLKID_MST_C_LRCLK_DIV 63 > +#define AUD_CLKID_MST_C_LRCLK 64 > +#define AUD_CLKID_MST_D_LRCLK_DIV 65 > +#define AUD_CLKID_MST_D_LRCLK 66 > +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67 > +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68 > +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69 > +#define AUD_CLKID_TDMIN_A_SCLK 70 > +#define AUD_CLKID_TDMIN_A_LRCLK 71 > +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72 > +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73 > +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74 > +#define AUD_CLKID_TDMIN_B_SCLK 75 > +#define AUD_CLKID_TDMIN_B_LRCLK 76 > +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77 > +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78 > +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79 > +#define AUD_CLKID_TDMIN_LB_SCLK 80 > +#define AUD_CLKID_TDMIN_LB_LRCLK 81 > +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82 > +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83 > +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84 > +#define AUD_CLKID_TDMOUT_A_SCLK 85 > +#define AUD_CLKID_TDMOUT_A_LRCLK 86 > +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87 > +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88 > +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89 > +#define AUD_CLKID_TDMOUT_B_SCLK 90 > +#define AUD_CLKID_TDMOUT_B_LRCLK 91 > + > +#define AUD_CLKID_VAD_DDR_ARB 1 > +#define AUD_CLKID_VAD_PDM 2 > +#define AUD_CLKID_VAD_TDMIN 3 > +#define AUD_CLKID_VAD_TODDR 4 > +#define AUD_CLKID_VAD 5 > +#define AUD_CLKID_VAD_AUDIOTOP 6 > +#define AUD_CLKID_VAD_MCLK_SEL 7 > +#define AUD_CLKID_VAD_MCLK_DIV 8 > +#define AUD_CLKID_VAD_MCLK 9 > +#define AUD_CLKID_VAD_CLK_SEL 10 > +#define AUD_CLKID_VAD_CLK_DIV 11 > +#define AUD_CLKID_VAD_CLK 12 > +#define AUD_CLKID_VAD_PDM_DCLK_SEL 13 > +#define AUD_CLKID_VAD_PDM_DCLK_DIV 14 > +#define AUD_CLKID_VAD_PDM_DCLK 15 > +#define AUD_CLKID_VAD_PDM_SYSCLK_SEL 16 > +#define AUD_CLKID_VAD_PDM_SYSCLK_DIV 17 > +#define AUD_CLKID_VAD_PDM_SYSCLK 18 > + > +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */ > diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h > new file mode 100644 > index 000000000000..653fddba1d8f > --- /dev/null > +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. > + * > + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> > + */ > + > +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H > +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H > + > +#define AUD_RESET_DDRARB 0 > +#define AUD_RESET_TDMIN_A 1 > +#define AUD_RESET_TDMIN_B 2 > +#define AUD_RESET_TDMIN_LB 3 > +#define AUD_RESET_LOOPBACK 4 > +#define AUD_RESET_TDMOUT_A 5 > +#define AUD_RESET_TDMOUT_B 6 > +#define AUD_RESET_FRDDR_A 7 > +#define AUD_RESET_FRDDR_B 8 > +#define AUD_RESET_TODDR_A 9 > +#define AUD_RESET_TODDR_B 10 > +#define AUD_RESET_SPDIFIN 11 > +#define AUD_RESET_RESAMPLE 12 > +#define AUD_RESET_EQDRC 13 > +#define AUD_RESET_LOCKER 14 > +#define AUD_RESET_TOACODEC 30 > +#define AUD_RESET_CLKTREE 31 > + > +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
On Fri 13 Sep 2024 at 15:11, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote: > Add device tree bindings for A1 SoC audio clock and reset controllers. > > Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> > --- > .../clock/amlogic,axg-audio-clkc.yaml | 3 + > .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ > .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ > 3 files changed, 154 insertions(+) > create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h > create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > index fd7982dd4cea..df9eb8ce28dc 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml > @@ -18,6 +18,8 @@ description: > properties: > compatible: > enum: > + - amlogic,a1-audio-clkc This controller is missing aud_top clock input coming from the vad controller, AFAICT. > + - amlogic,a1-audio-vad-clkc > - amlogic,axg-audio-clkc > - amlogic,g12a-audio-clkc > - amlogic,sm1-audio-clkc > @@ -114,6 +116,7 @@ allOf: > compatible: > contains: > enum: > + - amlogic,a1-audio-clkc > - amlogic,g12a-audio-clkc > - amlogic,sm1-audio-clkc > then: > diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h > new file mode 100644 > index 000000000000..6534d1878816 > --- /dev/null > +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h > @@ -0,0 +1,122 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. > + * > + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> > + */ > + > +#ifndef __A1_AUDIO_CLKC_BINDINGS_H > +#define __A1_AUDIO_CLKC_BINDINGS_H > + > +#define AUD_CLKID_DDR_ARB 1 > +#define AUD_CLKID_TDMIN_A 2 > +#define AUD_CLKID_TDMIN_B 3 > +#define AUD_CLKID_TDMIN_LB 4 > +#define AUD_CLKID_LOOPBACK 5 > +#define AUD_CLKID_TDMOUT_A 6 > +#define AUD_CLKID_TDMOUT_B 7 > +#define AUD_CLKID_FRDDR_A 8 > +#define AUD_CLKID_FRDDR_B 9 > +#define AUD_CLKID_TODDR_A 10 > +#define AUD_CLKID_TODDR_B 11 > +#define AUD_CLKID_SPDIFIN 12 > +#define AUD_CLKID_RESAMPLE 13 > +#define AUD_CLKID_EQDRC 14 > +#define AUD_CLKID_LOCKER 15 > +#define AUD_CLKID_MST_A_MCLK_SEL 16 > +#define AUD_CLKID_MST_A_MCLK_DIV 17 > +#define AUD_CLKID_MST_A_MCLK 18 > +#define AUD_CLKID_MST_B_MCLK_SEL 19 > +#define AUD_CLKID_MST_B_MCLK_DIV 20 > +#define AUD_CLKID_MST_B_MCLK 21 > +#define AUD_CLKID_MST_C_MCLK_SEL 22 > +#define AUD_CLKID_MST_C_MCLK_DIV 23 > +#define AUD_CLKID_MST_C_MCLK 24 > +#define AUD_CLKID_MST_D_MCLK_SEL 25 > +#define AUD_CLKID_MST_D_MCLK_DIV 26 > +#define AUD_CLKID_MST_D_MCLK 27 > +#define AUD_CLKID_SPDIFIN_CLK_SEL 28 > +#define AUD_CLKID_SPDIFIN_CLK_DIV 29 > +#define AUD_CLKID_SPDIFIN_CLK 30 > +#define AUD_CLKID_RESAMPLE_CLK_SEL 31 > +#define AUD_CLKID_RESAMPLE_CLK_DIV 32 > +#define AUD_CLKID_RESAMPLE_CLK 33 > +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34 > +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35 > +#define AUD_CLKID_LOCKER_IN_CLK 36 > +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37 > +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38 > +#define AUD_CLKID_LOCKER_OUT_CLK 39 > +#define AUD_CLKID_EQDRC_CLK_SEL 40 > +#define AUD_CLKID_EQDRC_CLK_DIV 41 > +#define AUD_CLKID_EQDRC_CLK 42 > +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43 > +#define AUD_CLKID_MST_A_SCLK_DIV 44 > +#define AUD_CLKID_MST_A_SCLK_POST_EN 45 > +#define AUD_CLKID_MST_A_SCLK 46 > +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47 > +#define AUD_CLKID_MST_B_SCLK_DIV 48 > +#define AUD_CLKID_MST_B_SCLK_POST_EN 49 > +#define AUD_CLKID_MST_B_SCLK 50 > +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51 > +#define AUD_CLKID_MST_C_SCLK_DIV 52 > +#define AUD_CLKID_MST_C_SCLK_POST_EN 53 > +#define AUD_CLKID_MST_C_SCLK 54 > +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55 > +#define AUD_CLKID_MST_D_SCLK_DIV 56 > +#define AUD_CLKID_MST_D_SCLK_POST_EN 57 > +#define AUD_CLKID_MST_D_SCLK 58 > +#define AUD_CLKID_MST_A_LRCLK_DIV 59 > +#define AUD_CLKID_MST_A_LRCLK 60 > +#define AUD_CLKID_MST_B_LRCLK_DIV 61 > +#define AUD_CLKID_MST_B_LRCLK 62 > +#define AUD_CLKID_MST_C_LRCLK_DIV 63 > +#define AUD_CLKID_MST_C_LRCLK 64 > +#define AUD_CLKID_MST_D_LRCLK_DIV 65 > +#define AUD_CLKID_MST_D_LRCLK 66 > +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67 > +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68 > +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69 > +#define AUD_CLKID_TDMIN_A_SCLK 70 > +#define AUD_CLKID_TDMIN_A_LRCLK 71 > +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72 > +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73 > +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74 > +#define AUD_CLKID_TDMIN_B_SCLK 75 > +#define AUD_CLKID_TDMIN_B_LRCLK 76 > +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77 > +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78 > +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79 > +#define AUD_CLKID_TDMIN_LB_SCLK 80 > +#define AUD_CLKID_TDMIN_LB_LRCLK 81 > +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82 > +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83 > +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84 > +#define AUD_CLKID_TDMOUT_A_SCLK 85 > +#define AUD_CLKID_TDMOUT_A_LRCLK 86 > +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87 > +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88 > +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89 > +#define AUD_CLKID_TDMOUT_B_SCLK 90 > +#define AUD_CLKID_TDMOUT_B_LRCLK 91 > + > +#define AUD_CLKID_VAD_DDR_ARB 1 > +#define AUD_CLKID_VAD_PDM 2 > +#define AUD_CLKID_VAD_TDMIN 3 > +#define AUD_CLKID_VAD_TODDR 4 > +#define AUD_CLKID_VAD 5 > +#define AUD_CLKID_VAD_AUDIOTOP 6 > +#define AUD_CLKID_VAD_MCLK_SEL 7 > +#define AUD_CLKID_VAD_MCLK_DIV 8 > +#define AUD_CLKID_VAD_MCLK 9 > +#define AUD_CLKID_VAD_CLK_SEL 10 > +#define AUD_CLKID_VAD_CLK_DIV 11 > +#define AUD_CLKID_VAD_CLK 12 > +#define AUD_CLKID_VAD_PDM_DCLK_SEL 13 > +#define AUD_CLKID_VAD_PDM_DCLK_DIV 14 > +#define AUD_CLKID_VAD_PDM_DCLK 15 > +#define AUD_CLKID_VAD_PDM_SYSCLK_SEL 16 > +#define AUD_CLKID_VAD_PDM_SYSCLK_DIV 17 > +#define AUD_CLKID_VAD_PDM_SYSCLK 18 > + > +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */ > diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h > new file mode 100644 > index 000000000000..653fddba1d8f > --- /dev/null > +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* > + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. > + * > + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> > + */ > + > +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H > +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H > + > +#define AUD_RESET_DDRARB 0 > +#define AUD_RESET_TDMIN_A 1 > +#define AUD_RESET_TDMIN_B 2 > +#define AUD_RESET_TDMIN_LB 3 > +#define AUD_RESET_LOOPBACK 4 > +#define AUD_RESET_TDMOUT_A 5 > +#define AUD_RESET_TDMOUT_B 6 > +#define AUD_RESET_FRDDR_A 7 > +#define AUD_RESET_FRDDR_B 8 > +#define AUD_RESET_TODDR_A 9 > +#define AUD_RESET_TODDR_B 10 > +#define AUD_RESET_SPDIFIN 11 > +#define AUD_RESET_RESAMPLE 12 > +#define AUD_RESET_EQDRC 13 > +#define AUD_RESET_LOCKER 14 > +#define AUD_RESET_TOACODEC 30 > +#define AUD_RESET_CLKTREE 31 > + > +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
On Tue 22 Oct 2024 at 11:34, Jerome Brunet <jbrunet@baylibre.com> wrote: > On Fri 13 Sep 2024 at 15:11, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote: > >> Add device tree bindings for A1 SoC audio clock and reset controllers. >> >> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> >> --- >> .../clock/amlogic,axg-audio-clkc.yaml | 3 + >> .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ >> .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ >> 3 files changed, 154 insertions(+) >> create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h >> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> index fd7982dd4cea..df9eb8ce28dc 100644 >> --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> @@ -18,6 +18,8 @@ description: >> properties: >> compatible: >> enum: >> + - amlogic,a1-audio-clkc > > This controller is missing aud_top clock input coming from the vad > controller, AFAICT. > You are passing it thourgh pclk so it is fine
On 10/22/24 11:45, Jerome Brunet wrote: > On Fri 13 Sep 2024 at 15:11, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote: > >> Add device tree bindings for A1 SoC audio clock and reset controllers. >> >> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> > > Reset and clock are now independent. > > Please split the patch and send the changes in the related series, > bindings before the driver change. > I can cut "include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h" header and send it at the same series with modifications to reset aux device. Is it correct? >> --- >> .../clock/amlogic,axg-audio-clkc.yaml | 3 + >> .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ >> .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ >> 3 files changed, 154 insertions(+) >> create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h >> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> index fd7982dd4cea..df9eb8ce28dc 100644 >> --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml >> @@ -18,6 +18,8 @@ description: >> properties: >> compatible: >> enum: >> + - amlogic,a1-audio-clkc >> + - amlogic,a1-audio-vad-clkc >> - amlogic,axg-audio-clkc >> - amlogic,g12a-audio-clkc >> - amlogic,sm1-audio-clkc >> @@ -114,6 +116,7 @@ allOf: >> compatible: >> contains: >> enum: >> + - amlogic,a1-audio-clkc >> - amlogic,g12a-audio-clkc >> - amlogic,sm1-audio-clkc >> then: >> diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h >> new file mode 100644 >> index 000000000000..6534d1878816 >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h >> @@ -0,0 +1,122 @@ >> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ >> +/* >> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. >> + * >> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> >> + */ >> + >> +#ifndef __A1_AUDIO_CLKC_BINDINGS_H >> +#define __A1_AUDIO_CLKC_BINDINGS_H >> + >> +#define AUD_CLKID_DDR_ARB 1 >> +#define AUD_CLKID_TDMIN_A 2 >> +#define AUD_CLKID_TDMIN_B 3 >> +#define AUD_CLKID_TDMIN_LB 4 >> +#define AUD_CLKID_LOOPBACK 5 >> +#define AUD_CLKID_TDMOUT_A 6 >> +#define AUD_CLKID_TDMOUT_B 7 >> +#define AUD_CLKID_FRDDR_A 8 >> +#define AUD_CLKID_FRDDR_B 9 >> +#define AUD_CLKID_TODDR_A 10 >> +#define AUD_CLKID_TODDR_B 11 >> +#define AUD_CLKID_SPDIFIN 12 >> +#define AUD_CLKID_RESAMPLE 13 >> +#define AUD_CLKID_EQDRC 14 >> +#define AUD_CLKID_LOCKER 15 >> +#define AUD_CLKID_MST_A_MCLK_SEL 16 >> +#define AUD_CLKID_MST_A_MCLK_DIV 17 >> +#define AUD_CLKID_MST_A_MCLK 18 >> +#define AUD_CLKID_MST_B_MCLK_SEL 19 >> +#define AUD_CLKID_MST_B_MCLK_DIV 20 >> +#define AUD_CLKID_MST_B_MCLK 21 >> +#define AUD_CLKID_MST_C_MCLK_SEL 22 >> +#define AUD_CLKID_MST_C_MCLK_DIV 23 >> +#define AUD_CLKID_MST_C_MCLK 24 >> +#define AUD_CLKID_MST_D_MCLK_SEL 25 >> +#define AUD_CLKID_MST_D_MCLK_DIV 26 >> +#define AUD_CLKID_MST_D_MCLK 27 >> +#define AUD_CLKID_SPDIFIN_CLK_SEL 28 >> +#define AUD_CLKID_SPDIFIN_CLK_DIV 29 >> +#define AUD_CLKID_SPDIFIN_CLK 30 >> +#define AUD_CLKID_RESAMPLE_CLK_SEL 31 >> +#define AUD_CLKID_RESAMPLE_CLK_DIV 32 >> +#define AUD_CLKID_RESAMPLE_CLK 33 >> +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34 >> +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35 >> +#define AUD_CLKID_LOCKER_IN_CLK 36 >> +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37 >> +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38 >> +#define AUD_CLKID_LOCKER_OUT_CLK 39 >> +#define AUD_CLKID_EQDRC_CLK_SEL 40 >> +#define AUD_CLKID_EQDRC_CLK_DIV 41 >> +#define AUD_CLKID_EQDRC_CLK 42 >> +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43 >> +#define AUD_CLKID_MST_A_SCLK_DIV 44 >> +#define AUD_CLKID_MST_A_SCLK_POST_EN 45 >> +#define AUD_CLKID_MST_A_SCLK 46 >> +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47 >> +#define AUD_CLKID_MST_B_SCLK_DIV 48 >> +#define AUD_CLKID_MST_B_SCLK_POST_EN 49 >> +#define AUD_CLKID_MST_B_SCLK 50 >> +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51 >> +#define AUD_CLKID_MST_C_SCLK_DIV 52 >> +#define AUD_CLKID_MST_C_SCLK_POST_EN 53 >> +#define AUD_CLKID_MST_C_SCLK 54 >> +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55 >> +#define AUD_CLKID_MST_D_SCLK_DIV 56 >> +#define AUD_CLKID_MST_D_SCLK_POST_EN 57 >> +#define AUD_CLKID_MST_D_SCLK 58 >> +#define AUD_CLKID_MST_A_LRCLK_DIV 59 >> +#define AUD_CLKID_MST_A_LRCLK 60 >> +#define AUD_CLKID_MST_B_LRCLK_DIV 61 >> +#define AUD_CLKID_MST_B_LRCLK 62 >> +#define AUD_CLKID_MST_C_LRCLK_DIV 63 >> +#define AUD_CLKID_MST_C_LRCLK 64 >> +#define AUD_CLKID_MST_D_LRCLK_DIV 65 >> +#define AUD_CLKID_MST_D_LRCLK 66 >> +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67 >> +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68 >> +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69 >> +#define AUD_CLKID_TDMIN_A_SCLK 70 >> +#define AUD_CLKID_TDMIN_A_LRCLK 71 >> +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72 >> +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73 >> +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74 >> +#define AUD_CLKID_TDMIN_B_SCLK 75 >> +#define AUD_CLKID_TDMIN_B_LRCLK 76 >> +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77 >> +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78 >> +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79 >> +#define AUD_CLKID_TDMIN_LB_SCLK 80 >> +#define AUD_CLKID_TDMIN_LB_LRCLK 81 >> +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82 >> +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83 >> +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84 >> +#define AUD_CLKID_TDMOUT_A_SCLK 85 >> +#define AUD_CLKID_TDMOUT_A_LRCLK 86 >> +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87 >> +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88 >> +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89 >> +#define AUD_CLKID_TDMOUT_B_SCLK 90 >> +#define AUD_CLKID_TDMOUT_B_LRCLK 91 >> + >> +#define AUD_CLKID_VAD_DDR_ARB 1 >> +#define AUD_CLKID_VAD_PDM 2 >> +#define AUD_CLKID_VAD_TDMIN 3 >> +#define AUD_CLKID_VAD_TODDR 4 >> +#define AUD_CLKID_VAD 5 >> +#define AUD_CLKID_VAD_AUDIOTOP 6 >> +#define AUD_CLKID_VAD_MCLK_SEL 7 >> +#define AUD_CLKID_VAD_MCLK_DIV 8 >> +#define AUD_CLKID_VAD_MCLK 9 >> +#define AUD_CLKID_VAD_CLK_SEL 10 >> +#define AUD_CLKID_VAD_CLK_DIV 11 >> +#define AUD_CLKID_VAD_CLK 12 >> +#define AUD_CLKID_VAD_PDM_DCLK_SEL 13 >> +#define AUD_CLKID_VAD_PDM_DCLK_DIV 14 >> +#define AUD_CLKID_VAD_PDM_DCLK 15 >> +#define AUD_CLKID_VAD_PDM_SYSCLK_SEL 16 >> +#define AUD_CLKID_VAD_PDM_SYSCLK_DIV 17 >> +#define AUD_CLKID_VAD_PDM_SYSCLK 18 >> + >> +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */ >> diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h >> new file mode 100644 >> index 000000000000..653fddba1d8f >> --- /dev/null >> +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h >> @@ -0,0 +1,29 @@ >> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ >> +/* >> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. >> + * >> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> >> + */ >> + >> +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H >> +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H >> + >> +#define AUD_RESET_DDRARB 0 >> +#define AUD_RESET_TDMIN_A 1 >> +#define AUD_RESET_TDMIN_B 2 >> +#define AUD_RESET_TDMIN_LB 3 >> +#define AUD_RESET_LOOPBACK 4 >> +#define AUD_RESET_TDMOUT_A 5 >> +#define AUD_RESET_TDMOUT_B 6 >> +#define AUD_RESET_FRDDR_A 7 >> +#define AUD_RESET_FRDDR_B 8 >> +#define AUD_RESET_TODDR_A 9 >> +#define AUD_RESET_TODDR_B 10 >> +#define AUD_RESET_SPDIFIN 11 >> +#define AUD_RESET_RESAMPLE 12 >> +#define AUD_RESET_EQDRC 13 >> +#define AUD_RESET_LOCKER 14 >> +#define AUD_RESET_TOACODEC 30 >> +#define AUD_RESET_CLKTREE 31 >> + >> +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */ >
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml index fd7982dd4cea..df9eb8ce28dc 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml @@ -18,6 +18,8 @@ description: properties: compatible: enum: + - amlogic,a1-audio-clkc + - amlogic,a1-audio-vad-clkc - amlogic,axg-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc @@ -114,6 +116,7 @@ allOf: compatible: contains: enum: + - amlogic,a1-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc then: diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h new file mode 100644 index 000000000000..6534d1878816 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> + */ + +#ifndef __A1_AUDIO_CLKC_BINDINGS_H +#define __A1_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_DDR_ARB 1 +#define AUD_CLKID_TDMIN_A 2 +#define AUD_CLKID_TDMIN_B 3 +#define AUD_CLKID_TDMIN_LB 4 +#define AUD_CLKID_LOOPBACK 5 +#define AUD_CLKID_TDMOUT_A 6 +#define AUD_CLKID_TDMOUT_B 7 +#define AUD_CLKID_FRDDR_A 8 +#define AUD_CLKID_FRDDR_B 9 +#define AUD_CLKID_TODDR_A 10 +#define AUD_CLKID_TODDR_B 11 +#define AUD_CLKID_SPDIFIN 12 +#define AUD_CLKID_RESAMPLE 13 +#define AUD_CLKID_EQDRC 14 +#define AUD_CLKID_LOCKER 15 +#define AUD_CLKID_MST_A_MCLK_SEL 16 +#define AUD_CLKID_MST_A_MCLK_DIV 17 +#define AUD_CLKID_MST_A_MCLK 18 +#define AUD_CLKID_MST_B_MCLK_SEL 19 +#define AUD_CLKID_MST_B_MCLK_DIV 20 +#define AUD_CLKID_MST_B_MCLK 21 +#define AUD_CLKID_MST_C_MCLK_SEL 22 +#define AUD_CLKID_MST_C_MCLK_DIV 23 +#define AUD_CLKID_MST_C_MCLK 24 +#define AUD_CLKID_MST_D_MCLK_SEL 25 +#define AUD_CLKID_MST_D_MCLK_DIV 26 +#define AUD_CLKID_MST_D_MCLK 27 +#define AUD_CLKID_SPDIFIN_CLK_SEL 28 +#define AUD_CLKID_SPDIFIN_CLK_DIV 29 +#define AUD_CLKID_SPDIFIN_CLK 30 +#define AUD_CLKID_RESAMPLE_CLK_SEL 31 +#define AUD_CLKID_RESAMPLE_CLK_DIV 32 +#define AUD_CLKID_RESAMPLE_CLK 33 +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34 +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35 +#define AUD_CLKID_LOCKER_IN_CLK 36 +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37 +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38 +#define AUD_CLKID_LOCKER_OUT_CLK 39 +#define AUD_CLKID_EQDRC_CLK_SEL 40 +#define AUD_CLKID_EQDRC_CLK_DIV 41 +#define AUD_CLKID_EQDRC_CLK 42 +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43 +#define AUD_CLKID_MST_A_SCLK_DIV 44 +#define AUD_CLKID_MST_A_SCLK_POST_EN 45 +#define AUD_CLKID_MST_A_SCLK 46 +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47 +#define AUD_CLKID_MST_B_SCLK_DIV 48 +#define AUD_CLKID_MST_B_SCLK_POST_EN 49 +#define AUD_CLKID_MST_B_SCLK 50 +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51 +#define AUD_CLKID_MST_C_SCLK_DIV 52 +#define AUD_CLKID_MST_C_SCLK_POST_EN 53 +#define AUD_CLKID_MST_C_SCLK 54 +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55 +#define AUD_CLKID_MST_D_SCLK_DIV 56 +#define AUD_CLKID_MST_D_SCLK_POST_EN 57 +#define AUD_CLKID_MST_D_SCLK 58 +#define AUD_CLKID_MST_A_LRCLK_DIV 59 +#define AUD_CLKID_MST_A_LRCLK 60 +#define AUD_CLKID_MST_B_LRCLK_DIV 61 +#define AUD_CLKID_MST_B_LRCLK 62 +#define AUD_CLKID_MST_C_LRCLK_DIV 63 +#define AUD_CLKID_MST_C_LRCLK 64 +#define AUD_CLKID_MST_D_LRCLK_DIV 65 +#define AUD_CLKID_MST_D_LRCLK 66 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67 +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68 +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69 +#define AUD_CLKID_TDMIN_A_SCLK 70 +#define AUD_CLKID_TDMIN_A_LRCLK 71 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72 +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73 +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74 +#define AUD_CLKID_TDMIN_B_SCLK 75 +#define AUD_CLKID_TDMIN_B_LRCLK 76 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77 +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78 +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79 +#define AUD_CLKID_TDMIN_LB_SCLK 80 +#define AUD_CLKID_TDMIN_LB_LRCLK 81 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82 +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83 +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84 +#define AUD_CLKID_TDMOUT_A_SCLK 85 +#define AUD_CLKID_TDMOUT_A_LRCLK 86 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87 +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88 +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89 +#define AUD_CLKID_TDMOUT_B_SCLK 90 +#define AUD_CLKID_TDMOUT_B_LRCLK 91 + +#define AUD_CLKID_VAD_DDR_ARB 1 +#define AUD_CLKID_VAD_PDM 2 +#define AUD_CLKID_VAD_TDMIN 3 +#define AUD_CLKID_VAD_TODDR 4 +#define AUD_CLKID_VAD 5 +#define AUD_CLKID_VAD_AUDIOTOP 6 +#define AUD_CLKID_VAD_MCLK_SEL 7 +#define AUD_CLKID_VAD_MCLK_DIV 8 +#define AUD_CLKID_VAD_MCLK 9 +#define AUD_CLKID_VAD_CLK_SEL 10 +#define AUD_CLKID_VAD_CLK_DIV 11 +#define AUD_CLKID_VAD_CLK 12 +#define AUD_CLKID_VAD_PDM_DCLK_SEL 13 +#define AUD_CLKID_VAD_PDM_DCLK_DIV 14 +#define AUD_CLKID_VAD_PDM_DCLK 15 +#define AUD_CLKID_VAD_PDM_SYSCLK_SEL 16 +#define AUD_CLKID_VAD_PDM_SYSCLK_DIV 17 +#define AUD_CLKID_VAD_PDM_SYSCLK 18 + +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h new file mode 100644 index 000000000000..653fddba1d8f --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H + +#define AUD_RESET_DDRARB 0 +#define AUD_RESET_TDMIN_A 1 +#define AUD_RESET_TDMIN_B 2 +#define AUD_RESET_TDMIN_LB 3 +#define AUD_RESET_LOOPBACK 4 +#define AUD_RESET_TDMOUT_A 5 +#define AUD_RESET_TDMOUT_B 6 +#define AUD_RESET_FRDDR_A 7 +#define AUD_RESET_FRDDR_B 8 +#define AUD_RESET_TODDR_A 9 +#define AUD_RESET_TODDR_B 10 +#define AUD_RESET_SPDIFIN 11 +#define AUD_RESET_RESAMPLE 12 +#define AUD_RESET_EQDRC 13 +#define AUD_RESET_LOCKER 14 +#define AUD_RESET_TOACODEC 30 +#define AUD_RESET_CLKTREE 31 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
Add device tree bindings for A1 SoC audio clock and reset controllers. Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> --- .../clock/amlogic,axg-audio-clkc.yaml | 3 + .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ 3 files changed, 154 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h