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[178.118.65.79]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42d9b054c4csm112094465e9.2.2024.09.16.06.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 06:14:05 -0700 (PDT) From: Theo Debrouwere X-Google-Original-From: Theo Debrouwere Received: from tdebrouw by voyager.localdomain with local (Exim 4.97) (envelope-from ) id 1sqBYK-0000000063P-3p9x; Mon, 16 Sep 2024 15:14:04 +0200 To: linux-amlogic@lists.infradead.org Cc: Theo Debrouwere Subject: [PATCH] drm/meson: disable line encoder before programming the gamma table Date: Mon, 16 Sep 2024 15:14:00 +0200 Message-ID: <20240916131400.23261-1-theo.debrouwere@faytech.de> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240916_061409_099334_5C3EB02D X-CRM114-Status: GOOD ( 12.40 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org There is a very rare bug, where the gamma table can't be written correctly. It is possible to write some entries into the gamma data port, after which the WR_RDY bit isn't set anymore. This causes a timeout in the code, and more entries will be written into the table. (each having their own timeout) There will be an image produced, but the colors will be completely off. The number of entries that can be written seems random. The issue seems to be solved if the line encoder is disabled before the table is programmed. Signed-off-by: Theo Debrouwere --- drivers/gpu/drm/meson/meson_encoder_dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c index 7816902f59075..15fd9df58ae4e 100644 --- a/drivers/gpu/drm/meson/meson_encoder_dsi.c +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c @@ -66,10 +66,11 @@ static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge, /* ENCL clock setup is handled by CCF */ meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode); - meson_encl_load_gamma(priv); writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + meson_encl_load_gamma(priv); + writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFIFO_EN, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));