From patchwork Wed Oct 2 10:48:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13819638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A1D4CF31B0 for ; Wed, 2 Oct 2024 10:58:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jO4Judy/US5pz0a13nmGAuRoG+xy6DrI/YOow2BrsHE=; b=U91vB96Rb9js7T BnpZ0sd8RgFYgUnI+JZ2NjTnrvHMCdnujVv/iy/LsZqS1a58XIJfBmtvADOYMfhCgaydDcrVSgg4l 16TGuP7LdAv9JeLUv7y6Eksd6uDHpKKFEuwm8MTLnMVZRtsMvutHQEUMgN5aXq84tcxAblr1LwAkw rbjNtr3VQ2lPamyrAsUb+BQMBBDgCYatHfXjVYtnhuImnK979ca2Igq9f4g/QZJjUSMpyDKq42nYw xZF3TBNsIMmV6XaOUkoKSWIw+yLv1tqTMHDyGeQHSbzmmYtkUnl5s1cPBjXsY9seg6+AziH7qzirG G22+st8IgBiqD+9/VAOA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svx4C-00000005aCW-0Eok; Wed, 02 Oct 2024 10:58:48 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1svwuU-00000005XwA-1n7j; Wed, 02 Oct 2024 10:48:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id C86495C0114; Wed, 2 Oct 2024 10:48:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18D35C4CEC5; Wed, 2 Oct 2024 10:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866125; bh=OO6xrEZafxMp0b36XkiEjc5EYx9OU0Q2uYuiCSv6Bso=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y3OYByTYNpeaweqY/uQo1qtt3imPJqkjeT1vrakSOBDnNQLT/jEcuii0gSq5E2RLc xs2kIY++mflSWoyWTNGvVRLs0IVHchAKEMe4SrDR0oUTW+4zX/D7QijdMJQ0Q1ujjH OdS/Sb7oEiRq2Z8Zxs5HL3fvJvBVD1A3cxPahAsNRUtKnUM1S1olSXeZsqv/2op/Vs kY6+TCXv9jX59XNQbT3FnGhEWKWieqvbEFQrmUgy05H450DmU/W3uWCAacnqZWJQO+ nwCjNARtdbDZi6xxntkf8LPjDbyCvHGnYn+OrAKlfIb4VtPZ7HpoiMQsm6ZlXfW/m4 Uq6aitmrzDvGw== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 07/11] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Wed, 2 Oct 2024 11:48:05 +0100 Message-ID: <20241002-alarm-drop-down-e37c31e50a48@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3114; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=kST0+2tXhuKzMDOPomFGGrXe4L7ZWEEe3gXv+x0OOeE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR6Wt12Ydeai+CKLbVtPx9pPuv5iTbpzIZ+P1slN1 RwRLDv/dpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAigqsZGe7tOFrA8qh5p8KJ T4m/jBYUd59NnfbRes3F4lm2FRFnC24x/E9tcxaatEbS8bqBJFPxzCTmL1c+1VizrGZfv+mjypw LV1kA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_034846_586389_3A22815D X-CRM114-Status: GOOD ( 12.29 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2a..ee4f31596d978 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and reset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of the mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells = <2>; - #size-cells = <2>; - clkcfg: clock-controller@20002000 { + #address-cells = <1>; + #size-cells = <1>; + + clkcfg: clock-controller@3E001000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + reg = <0x3E001000 0x1000>; clocks = <&ref>; #clock-cells = <1>; };