@@ -33,6 +33,10 @@ menuconfig COMMON_CLK
if COMMON_CLK
+config COMMON_CLK_REGMAP
+ bool
+ select REGMAP
+
config COMMON_CLK_WM831X
tristate "Clock driver for WM831x/2x PMICs"
depends on MFD_WM831X
@@ -14,6 +14,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-gate.o
obj-$(CONFIG_CLK_GATE_KUNIT_TEST) += clk-gate_test.o
obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o
+obj-$(CONFIG_COMMON_CLK_REGMAP) += clk-regmap.o
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
obj-$(CONFIG_CLK_FD_KUNIT_TEST) += clk-fractional-divider_test.o
similarity index 99%
rename from drivers/clk/meson/clk-regmap.c
rename to drivers/clk/clk-regmap.c
@@ -5,7 +5,7 @@
*/
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
{
@@ -2,61 +2,57 @@
menu "Clock support for Amlogic platforms"
depends on ARCH_MESON || COMPILE_TEST
-config COMMON_CLK_MESON_REGMAP
- tristate
- select REGMAP
-
config COMMON_CLK_MESON_DUALDIV
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_MPLL
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_PHASE
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_PLL
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_SCLK_DIV
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_VID_PLL_DIV
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_VCLK
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON_CLKC_UTILS
tristate
config COMMON_CLK_MESON_AO_CLKC
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select RESET_CONTROLLER
config COMMON_CLK_MESON_EE_CLKC
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
config COMMON_CLK_MESON_CPU_DYNDIV
tristate
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
config COMMON_CLK_MESON8B
bool "Meson8 SoC Clock controller support"
depends on ARM
default y
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
@@ -71,7 +67,7 @@ config COMMON_CLK_GXBB
tristate "GXBB and GXL SoC clock controllers support"
depends on ARM64
default y
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_VID_PLL_DIV
select COMMON_CLK_MESON_MPLL
@@ -87,7 +83,7 @@ config COMMON_CLK_AXG
tristate "AXG SoC clock controllers support"
depends on ARM64
default y
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
@@ -101,7 +97,7 @@ config COMMON_CLK_AXG
config COMMON_CLK_AXG_AUDIO
tristate "Meson AXG Audio Clock Controller Driver"
depends on ARM64
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_PHASE
select COMMON_CLK_MESON_SCLK_DIV
select COMMON_CLK_MESON_CLKC_UTILS
@@ -113,7 +109,7 @@ config COMMON_CLK_AXG_AUDIO
config COMMON_CLK_A1_PLL
tristate "Amlogic A1 SoC PLL controller support"
depends on ARM64
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_PLL
help
@@ -125,7 +121,7 @@ config COMMON_CLK_A1_PERIPHERALS
tristate "Amlogic A1 SoC Peripherals clock controller support"
depends on ARM64
select COMMON_CLK_MESON_DUALDIV
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
help
Support for the Peripherals clock controller on Amlogic A113L based
@@ -136,7 +132,7 @@ config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64
default y
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_PLL
select COMMON_CLK_MESON_CLKC_UTILS
imply COMMON_CLK_SCMI
@@ -149,7 +145,7 @@ config COMMON_CLK_C3_PERIPHERALS
tristate "Amlogic C3 peripherals clock controller"
depends on ARM64
default y
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_CLKC_UTILS
imply COMMON_CLK_SCMI
@@ -163,7 +159,7 @@ config COMMON_CLK_G12A
tristate "G12 and SM1 SoC clock controllers support"
depends on ARM64
default y
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
@@ -184,7 +180,7 @@ config COMMON_CLK_S4_PLL
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
help
Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices,
AKA S4. Say Y if you want the board to work, because PLLs are the parent of
@@ -195,7 +191,7 @@ config COMMON_CLK_S4_PERIPHERALS
depends on ARM64
default y
select COMMON_CLK_MESON_CLKC_UTILS
- select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_REGMAP
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_VID_PLL_DIV
help
@@ -9,7 +9,6 @@ obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
-obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
@@ -12,7 +12,7 @@
#include <linux/platform_device.h>
#include "a1-peripherals.h"
#include "clk-dualdiv.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
@@ -11,7 +11,7 @@
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-pll.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
@@ -15,7 +15,7 @@
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-dualdiv.h"
#include <dt-bindings/clock/axg-aoclkc.h>
@@ -17,7 +17,7 @@
#include "meson-clkc-utils.h"
#include "axg-audio.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-phase.h"
#include "sclk-div.h"
@@ -15,7 +15,7 @@
#include <linux/platform_device.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-pll.h"
#include "clk-mpll.h"
#include "axg.h"
@@ -8,7 +8,7 @@
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-dualdiv.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
@@ -8,7 +8,7 @@
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-pll.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
@@ -7,7 +7,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-cpu-dyndiv.h"
static inline struct meson_clk_cpu_dyndiv_data *
@@ -24,7 +24,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-dualdiv.h"
static inline struct meson_clk_dualdiv_data *
@@ -15,7 +15,7 @@
#include <linux/module.h>
#include <linux/spinlock.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-mpll.h"
#define SDM_DEN 16384
@@ -7,7 +7,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-phase.h"
#define phase_step(_width) (360 / (1 << (_width)))
@@ -33,7 +33,7 @@
#include <linux/math64.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-pll.h"
static inline struct meson_clk_pll_data *
@@ -15,7 +15,7 @@
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-dualdiv.h"
#include <dt-bindings/clock/g12a-aoclkc.h>
@@ -19,7 +19,7 @@
#include "clk-mpll.h"
#include "clk-pll.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-cpu-dyndiv.h"
#include "vid-pll-div.h"
#include "vclk.h"
@@ -8,7 +8,7 @@
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-dualdiv.h"
#include <dt-bindings/clock/gxbb-aoclkc.h>
@@ -11,7 +11,7 @@
#include <linux/module.h>
#include "gxbb.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-pll.h"
#include "clk-mpll.h"
#include "meson-eeclk.h"
@@ -16,7 +16,7 @@
#include <linux/regmap.h>
#include <linux/reset-controller.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "meson-clkc-utils.h"
struct meson_aoclk_data {
@@ -11,7 +11,7 @@
#include <linux/regmap.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "meson-eeclk.h"
int meson_eeclkc_probe(struct platform_device *pdev)
@@ -8,7 +8,7 @@
#define __MESON_CLKC_H
#include <linux/clk-provider.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "meson-clkc-utils.h"
struct platform_device;
@@ -10,7 +10,7 @@
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "clk-pll.h"
#define AM_DDR_PLL_CNTL 0x00
@@ -17,7 +17,7 @@
#include <linux/regmap.h>
#include "meson8b.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "meson-clkc-utils.h"
#include "clk-pll.h"
#include "clk-mpll.h"
@@ -10,7 +10,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "vid-pll-div.h"
#include "clk-dualdiv.h"
#include "s4-peripherals.h"
@@ -12,7 +12,7 @@
#include "clk-mpll.h"
#include "clk-pll.h"
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "s4-pll.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
@@ -19,7 +19,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "sclk-div.h"
static inline struct meson_sclk_div_data *
@@ -6,7 +6,7 @@
#ifndef __VCLK_H
#define __VCLK_H
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "parm.h"
/**
@@ -7,7 +7,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include "clk-regmap.h"
+#include <linux/clk/clk-regmap.h>
#include "vid-pll-div.h"
static inline struct meson_vid_pll_div_data *
similarity index 100%
rename from drivers/clk/meson/clk-regmap.h
rename to include/linux/clk/clk-regmap.h