| Message ID | 20241002-unvaried-clever-374b4d763849@spud (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Redo PolarFire SoC's mailbox/clock devicestrees and related code | expand |
On Wed, Oct 02, 2024 at 11:48:02AM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > There are two syscons on PolarFire SoC that provide various functionality of > use to the OS. > > The first of these is the "control-scb" region, that contains the "tvs" > temperature and voltage sensors and the control/status registers for the > system controller's mailbox. The mailbox has a dedicated node, so > there's no need for a child node describing it, looking the syscon up by > compatible is sufficient. > > The second, "mss-top-sysreg", contains clocks, pinctrl, resets, and > interrupt controller and more. At this point, only the reset controller > child is described as that's all that is described by the existing > bindings. The clock controller already has a dedicated node, and will > retain it as there are other clock regions, so like the mailbox, > a compatible-based lookup of the syscon is sufficient to keep the clock > driver working as before so no child is needed. There's also an > interrupt multiplexing service provided by this syscon, for which there > is work in progress at [1]. > > Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a4fefe@wendy/ [1] > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../microchip/microchip,mpfs-control-scb.yaml | 44 +++++++++++++++ > .../microchip,mpfs-mss-top-sysreg.yaml | 54 +++++++++++++++++++ > 2 files changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml > create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml > > diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml > new file mode 100644 > index 0000000000000..4f9168320243c > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml > @@ -0,0 +1,44 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-control-scb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PolarFire SoC System Controller Bus (SCB) Control Register region > + > +maintainers: > + - Conor Dooley <conor.dooley@microchip.com> > + > +description: > + An assortment of system controller related registers, including voltage and > + temperature sensors and the status/control registers for the system > + controller's mailbox. > + > +properties: > + compatible: > + items: > + - const: microchip,mpfs-control-scb > + - const: syscon > + - const: simple-mfd Where's the child nodes? > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <1>; > + #size-cells = <1>; Don't need the soc node. > + > + syscon@37020000 { > + compatible = "microchip,mpfs-control-scb", "syscon", "simple-mfd"; > + reg = <0x37020000 0x100>; > + }; > + }; > + > diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml > new file mode 100644 > index 0000000000000..98ccec3caad51 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg Register region > + > +maintainers: > + - Conor Dooley <conor.dooley@microchip.com> > + > +description: > + An wide assortment of registers that control elements of the MSS on PolarFire > + SoC, including pinmuxing, resets and clocks among others. > + > +properties: > + compatible: > + items: > + - const: microchip,mpfs-mss-top-sysreg > + - const: syscon > + - const: simple-mfd > + > + reg: > + maxItems: 1 > + > + '#reset-cells': > + description: | Don't need '|'. > + The AHB/AXI peripherals on the PolarFire SoC have reset support, so > + from CLK_ENVM to CLK_CFM. The reset consumer should specify the > + desired peripheral via the clock ID in its "resets" phandle cell. > + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list > + of PolarFire clock/reset IDs. > + const: 1 > + > +required: > + - compatible > + - reg > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + > + syscon@20002000 { > + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; > + reg = <0x20002000 0x1000>; > + #reset-cells = <1>; > + }; > + }; > + > -- > 2.45.2 >
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml new file mode 100644 index 0000000000000..4f9168320243c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-control-scb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC System Controller Bus (SCB) Control Register region + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: + An assortment of system controller related registers, including voltage and + temperature sensors and the status/control registers for the system + controller's mailbox. + +properties: + compatible: + items: + - const: microchip,mpfs-control-scb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + syscon@37020000 { + compatible = "microchip,mpfs-control-scb", "syscon", "simple-mfd"; + reg = <0x37020000 0x100>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 0000000000000..98ccec3caad51 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg Register region + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: + An wide assortment of registers that control elements of the MSS on PolarFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#reset-cells': + description: | + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list + of PolarFire clock/reset IDs. + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + syscon@20002000 { + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg = <0x20002000 0x1000>; + #reset-cells = <1>; + }; + }; +