@@ -18,6 +18,8 @@ description:
properties:
compatible:
enum:
+ - amlogic,a1-audio-clkc
+ - amlogic,a1-audio-vad-clkc
- amlogic,axg-audio-clkc
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
@@ -114,6 +116,8 @@ allOf:
compatible:
contains:
enum:
+ - amlogic,a1-audio-clkc
+ - amlogic,a1-audio-vad-clkc
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
then:
new file mode 100644
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef __A1_AUDIO_CLKC_BINDINGS_H
+#define __A1_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB 1
+#define AUD_CLKID_TDMIN_A 2
+#define AUD_CLKID_TDMIN_B 3
+#define AUD_CLKID_TDMIN_LB 4
+#define AUD_CLKID_LOOPBACK 5
+#define AUD_CLKID_TDMOUT_A 6
+#define AUD_CLKID_TDMOUT_B 7
+#define AUD_CLKID_FRDDR_A 8
+#define AUD_CLKID_FRDDR_B 9
+#define AUD_CLKID_TODDR_A 10
+#define AUD_CLKID_TODDR_B 11
+#define AUD_CLKID_SPDIFIN 12
+#define AUD_CLKID_RESAMPLE 13
+#define AUD_CLKID_EQDRC 14
+#define AUD_CLKID_LOCKER 15
+#define AUD_CLKID_MST_A_MCLK_SEL 16
+#define AUD_CLKID_MST_A_MCLK_DIV 17
+#define AUD_CLKID_MST_A_MCLK 18
+#define AUD_CLKID_MST_B_MCLK_SEL 19
+#define AUD_CLKID_MST_B_MCLK_DIV 20
+#define AUD_CLKID_MST_B_MCLK 21
+#define AUD_CLKID_MST_C_MCLK_SEL 22
+#define AUD_CLKID_MST_C_MCLK_DIV 23
+#define AUD_CLKID_MST_C_MCLK 24
+#define AUD_CLKID_MST_D_MCLK_SEL 25
+#define AUD_CLKID_MST_D_MCLK_DIV 26
+#define AUD_CLKID_MST_D_MCLK 27
+#define AUD_CLKID_MST_A_SCLK_PRE_EN 28
+#define AUD_CLKID_MST_A_SCLK_DIV 29
+#define AUD_CLKID_MST_A_SCLK_POST_EN 30
+#define AUD_CLKID_MST_A_SCLK 31
+#define AUD_CLKID_MST_B_SCLK_PRE_EN 32
+#define AUD_CLKID_MST_B_SCLK_DIV 33
+#define AUD_CLKID_MST_B_SCLK_POST_EN 34
+#define AUD_CLKID_MST_B_SCLK 35
+#define AUD_CLKID_MST_C_SCLK_PRE_EN 36
+#define AUD_CLKID_MST_C_SCLK_DIV 37
+#define AUD_CLKID_MST_C_SCLK_POST_EN 38
+#define AUD_CLKID_MST_C_SCLK 39
+#define AUD_CLKID_MST_D_SCLK_PRE_EN 40
+#define AUD_CLKID_MST_D_SCLK_DIV 41
+#define AUD_CLKID_MST_D_SCLK_POST_EN 42
+#define AUD_CLKID_MST_D_SCLK 43
+#define AUD_CLKID_MST_A_LRCLK_DIV 44
+#define AUD_CLKID_MST_A_LRCLK 45
+#define AUD_CLKID_MST_B_LRCLK_DIV 46
+#define AUD_CLKID_MST_B_LRCLK 47
+#define AUD_CLKID_MST_C_LRCLK_DIV 48
+#define AUD_CLKID_MST_C_LRCLK 49
+#define AUD_CLKID_MST_D_LRCLK_DIV 50
+#define AUD_CLKID_MST_D_LRCLK 51
+#define AUD_CLKID_TDMIN_A_SCLK_SEL 52
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 53
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 54
+#define AUD_CLKID_TDMIN_A_SCLK 55
+#define AUD_CLKID_TDMIN_A_LRCLK 56
+#define AUD_CLKID_TDMIN_B_SCLK_SEL 57
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 58
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 59
+#define AUD_CLKID_TDMIN_B_SCLK 60
+#define AUD_CLKID_TDMIN_B_LRCLK 61
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL 62
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 63
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 64
+#define AUD_CLKID_TDMIN_LB_SCLK 65
+#define AUD_CLKID_TDMIN_LB_LRCLK 66
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL 67
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 68
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 69
+#define AUD_CLKID_TDMOUT_A_SCLK 70
+#define AUD_CLKID_TDMOUT_A_LRCLK 71
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL 72
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 73
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 74
+#define AUD_CLKID_TDMOUT_B_SCLK 75
+#define AUD_CLKID_TDMOUT_B_LRCLK 76
+#define AUD_CLKID_SPDIFIN_CLK_SEL 77
+#define AUD_CLKID_SPDIFIN_CLK_DIV 78
+#define AUD_CLKID_SPDIFIN_CLK 79
+#define AUD_CLKID_RESAMPLE_CLK_SEL 80
+#define AUD_CLKID_RESAMPLE_CLK_DIV 81
+#define AUD_CLKID_RESAMPLE_CLK 82
+#define AUD_CLKID_EQDRC_CLK_SEL 83
+#define AUD_CLKID_EQDRC_CLK_DIV 84
+#define AUD_CLKID_EQDRC_CLK 85
+#define AUD_CLKID_LOCKER_IN_CLK_SEL 86
+#define AUD_CLKID_LOCKER_IN_CLK_DIV 87
+#define AUD_CLKID_LOCKER_IN_CLK 88
+#define AUD_CLKID_LOCKER_OUT_CLK_SEL 89
+#define AUD_CLKID_LOCKER_OUT_CLK_DIV 90
+#define AUD_CLKID_LOCKER_OUT_CLK 91
+
+#define AUD_VAD_CLKID_CLK81 1
+#define AUD_VAD_CLKID_SYSCLK_A_DIV 2
+#define AUD_VAD_CLKID_SYSCLK_A 3
+#define AUD_VAD_CLKID_SYSCLK_B_DIV 4
+#define AUD_VAD_CLKID_SYSCLK_B 5
+#define AUD_VAD_CLKID_SYSCLK 6
+#define AUD_VAD_CLKID_DDR_ARB 7
+#define AUD_VAD_CLKID_PDM 8
+#define AUD_VAD_CLKID_TDMIN_VAD 9
+#define AUD_VAD_CLKID_TODDR_VAD 10
+#define AUD_VAD_CLKID_TOVAD 11
+#define AUD_VAD_CLKID_TOAUDIOTOP 12
+#define AUD_VAD_CLKID_MST_VAD_MCLK_SEL 13
+#define AUD_VAD_CLKID_MST_VAD_MCLK_DIV 14
+#define AUD_VAD_CLKID_MST_VAD_MCLK 15
+#define AUD_VAD_CLKID_MST_VAD_SCLK_PRE_EN 16
+#define AUD_VAD_CLKID_MST_VAD_SCLK_DIV 17
+#define AUD_VAD_CLKID_MST_VAD_SCLK_POST_EN 18
+#define AUD_VAD_CLKID_MST_VAD_SCLK 19
+#define AUD_VAD_CLKID_MST_VAD_LRCLK_DIV 20
+#define AUD_VAD_CLKID_MST_VAD_LRCLK 21
+#define AUD_VAD_CLKID_TDMIN_VAD_SCLK_SEL 22
+#define AUD_VAD_CLKID_TDMIN_VAD_SCLK_PRE_EN 23
+#define AUD_VAD_CLKID_TDMIN_VAD_SCLK_POST_EN 24
+#define AUD_VAD_CLKID_TDMIN_VAD_SCLK 25
+#define AUD_VAD_CLKID_TDMIN_VAD_LRCLK 26
+#define AUD_VAD_CLKID_PDM_DCLK_SEL 27
+#define AUD_VAD_CLKID_PDM_DCLK_DIV 28
+#define AUD_VAD_CLKID_PDM_DCLK 29
+#define AUD_VAD_CLKID_PDM_SYSCLK_SEL 30
+#define AUD_VAD_CLKID_PDM_SYSCLK_DIV 31
+#define AUD_VAD_CLKID_PDM_SYSCLK 32
+#define AUD_VAD_CLKID_VAD_CLK_SEL 33
+#define AUD_VAD_CLKID_VAD_CLK_DIV 34
+#define AUD_VAD_CLKID_VAD_CLK 35
+
+#endif /* __A1_AUDIO_CLKC_BINDINGS_H */
Add device tree bindings for A1 SoC audio clock and reset controllers. Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> --- .../clock/amlogic,axg-audio-clkc.yaml | 4 + .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 139 ++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h