| Message ID | 20250403-dt-cpu-schema-v1-3-076be7171a85@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Arm cpu schema clean-ups | expand |
On 4/4/25 04:59, Rob Herring (Arm) wrote: > There's no need include the CPU number in the L2 cache node names as > the names are local to the CPU nodes. The documented node name is > also just "l2-cache". > > The L3 cache is not part of cpu@0/l2-cache as it is shared among all > cores. Move it to /cpus node which is the typical place for shared > caches. > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org> > --- > arch/arm64/boot/dts/arm/morello.dtsi | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On Thu, 03 Apr 2025 21:59:21 -0500, Rob Herring (Arm) wrote: > The Arm cpu.yaml schema fails to restrict allowed properties in 'cpu' > nodes. The result, not surprisely, is a number of additional properties > and errors in .dts files. This series resolves those issues. > > There's still more properties in arm32 DTS files which I have not > documented. Mostly yet more supply names and "fsl,soc-operating-points". > What's a few more warnings on the 10000s of warnings... > > [...] Applied to sudeep.holla/linux (for-next/juno/fixes), thanks! [03/19] arm64: dts: morello: Fix-up cache nodes https://git.kernel.org/sudeep.holla/c/0c562281199f -- Regards, Sudeep
diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi index 0bab0b3ea969..5bc1c725dc86 100644 --- a/arch/arm64/boot/dts/arm/morello.dtsi +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -44,7 +44,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; clocks = <&scmi_dvfs 0>; - l2_0: l2-cache-0 { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -53,13 +53,6 @@ l2_0: l2-cache-0 { cache-sets = <2048>; cache-unified; next-level-cache = <&l3_0>; - - l3_0: l3-cache { - compatible = "cache"; - cache-level = <3>; - cache-size = <0x100000>; - cache-unified; - }; }; }; @@ -78,7 +71,7 @@ cpu1: cpu@100 { next-level-cache = <&l2_1>; clocks = <&scmi_dvfs 0>; - l2_1: l2-cache-1 { + l2_1: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -105,7 +98,7 @@ cpu2: cpu@10000 { next-level-cache = <&l2_2>; clocks = <&scmi_dvfs 1>; - l2_2: l2-cache-2 { + l2_2: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -132,7 +125,7 @@ cpu3: cpu@10100 { next-level-cache = <&l2_3>; clocks = <&scmi_dvfs 1>; - l2_3: l2-cache-3 { + l2_3: l2-cache { compatible = "cache"; cache-level = <2>; /* 8 ways set associative */ @@ -143,6 +136,13 @@ l2_3: l2-cache-3 { next-level-cache = <&l3_0>; }; }; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x100000>; + cache-unified; + }; }; firmware {
There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". The L3 cache is not part of cpu@0/l2-cache as it is shared among all cores. Move it to /cpus node which is the typical place for shared caches. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> --- arch/arm64/boot/dts/arm/morello.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)