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[GIT,PULL] clk: meson: update for v5.3

Message ID 39ccc93ddd8bc64af85541086190e563fa13f038.camel@baylibre.com (mailing list archive)
State Not Applicable
Headers show
Series [GIT,PULL] clk: meson: update for v5.3 | expand

Pull-request

git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1

Message

Jerome Brunet June 11, 2019, 12:38 p.m. UTC
Dear clock maintainers,

Below is a request to pull Amlogic clock update for v5.3 based on the fixes
we just send. This update add the init() callback to the mpll clock driver
as discussed in the previous cycle. As promised, the rework to register/deregister
will follow.

Apart from this, we've got a fairly regular update, adding a bunch of new
clocks to several SoC families. It also adds support for g12b derived from the
g12a, which explains the significant line count in the g12a file.

The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c:

  clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1

for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db:

  clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200)

----------------------------------------------------------------
Fix mpll fractional part and spread sprectrum issues
Add meson8 audio clocks
Add g12a temperature sensors clocks
Add g12a and g12b cpu clocks

----------------------------------------------------------------
Guillaume La Roque (2):
      dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
      clk: meson-g12a: add temperature sensor clocks

Jerome Brunet (10):
      clk: meson: mpll: properly handle spread spectrum
      clk: meson: gxbb: no spread spectrum on mpll0
      clk: meson: axg: spread spectrum is on mpll2
      clk: meson: mpll: add init callback and regs
      clk: meson: g12a: add mpll register init sequences
      clk: meson: eeclk: add init regs
      clk: meson: g12a: add controller register init
      Merge branch 'v5.3/dt' into v5.3/drivers
      Merge branch 'v5.3/dt' into v5.3/drivers
      Merge branch 'v5.3/dt' into v5.3/drivers

Martin Blumenstingl (4):
      dt-bindings: clock: meson8b: add the audio clocks
      clk: meson: meson8b: add the cts_amclk clocks
      clk: meson: meson8b: add the cts_mclk_i958 clocks
      clk: meson: meson8b: add the cts_i958 clock

Neil Armstrong (3):
      dt-bindings: clk: meson: add g12b periph clock controller bindings
      clk: meson: g12a: Add support for G12B CPUB clocks
      clk: meson: g12a: mark fclk_div3 as critical

 .../bindings/clock/amlogic,gxbb-clkc.txt           |   1 +
 drivers/clk/meson/axg.c                            |  10 +-
 drivers/clk/meson/clk-mpll.c                       |  36 +-
 drivers/clk/meson/clk-mpll.h                       |   3 +
 drivers/clk/meson/g12a.c                           | 843 ++++++++++++++++++++-
 drivers/clk/meson/g12a.h                           |  41 +-
 drivers/clk/meson/gxbb.c                           |   5 -
 drivers/clk/meson/meson-eeclk.c                    |   3 +
 drivers/clk/meson/meson-eeclk.h                    |   2 +
 drivers/clk/meson/meson8b.c                        | 154 ++++
 drivers/clk/meson/meson8b.h                        |   8 +-
 include/dt-bindings/clock/g12a-clkc.h              |   1 +
 include/dt-bindings/clock/meson8b-clkc.h           |   3 +
 13 files changed, 1083 insertions(+), 27 deletions(-)

Comments

Stephen Boyd June 25, 2019, 12:47 a.m. UTC | #1
Quoting Jerome Brunet (2019-06-11 05:38:17)
> Dear clock maintainers,
> 
> Below is a request to pull Amlogic clock update for v5.3 based on the fixes
> we just send. This update add the init() callback to the mpll clock driver
> as discussed in the previous cycle. As promised, the rework to register/deregister
> will follow.
> 
> Apart from this, we've got a fairly regular update, adding a bunch of new
> clocks to several SoC families. It also adds support for g12b derived from the
> g12a, which explains the significant line count in the g12a file.
> 
> The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c:
> 
>   clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200)
> 
> are available in the Git repository at:
> 
>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1
> 
> for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db:
> 
>   clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200)
> 
> ----------------------------------------------------------------

Thanks. Pulled into clk-next
Jerome Brunet June 25, 2019, 8:56 a.m. UTC | #2
On Tue 11 Jun 2019 at 14:38, Jerome Brunet <jbrunet@baylibre.com> wrote:

> Dear clock maintainers,
>
> Below is a request to pull Amlogic clock update for v5.3 based on the fixes
> we just send. This update add the init() callback to the mpll clock driver
> as discussed in the previous cycle. As promised, the rework to register/deregister
> will follow.
>
> Apart from this, we've got a fairly regular update, adding a bunch of new
> clocks to several SoC families. It also adds support for g12b derived from the
> g12a, which explains the significant line count in the g12a file.
>
> The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c:
>
>   clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200)
>
> are available in the Git repository at:
>
>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1
>
> for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db:
>
>   clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200)
>

Hi Stephen,

Could let us if you intend to take this PR as it is or if you are expecting
any change ?

Best regards
Jerome
Jerome Brunet June 25, 2019, 9:26 a.m. UTC | #3
On Tue 25 Jun 2019 at 10:56, Jerome Brunet <jbrunet@baylibre.com> wrote:

> On Tue 11 Jun 2019 at 14:38, Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>> Dear clock maintainers,
>>
>> Below is a request to pull Amlogic clock update for v5.3 based on the fixes
>> we just send. This update add the init() callback to the mpll clock driver
>> as discussed in the previous cycle. As promised, the rework to register/deregister
>> will follow.
>>
>> Apart from this, we've got a fairly regular update, adding a bunch of new
>> clocks to several SoC families. It also adds support for g12b derived from the
>> g12a, which explains the significant line count in the g12a file.
>>
>> The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c:
>>
>>   clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200)
>>
>> are available in the Git repository at:
>>
>>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1
>>
>> for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db:
>>
>>   clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200)
>>
>
> Hi Stephen,
>
> Could let us if you intend to take this PR as it is or if you are expecting
> any change ?
>
> Best regards
> Jerome

Nevermind, I missed your reply.
Thanks for merging.

Regards