Message ID | 39ccc93ddd8bc64af85541086190e563fa13f038.camel@baylibre.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
Series | [GIT,PULL] clk: meson: update for v5.3 | expand |
Quoting Jerome Brunet (2019-06-11 05:38:17) > Dear clock maintainers, > > Below is a request to pull Amlogic clock update for v5.3 based on the fixes > we just send. This update add the init() callback to the mpll clock driver > as discussed in the previous cycle. As promised, the rework to register/deregister > will follow. > > Apart from this, we've got a fairly regular update, adding a bunch of new > clocks to several SoC families. It also adds support for g12b derived from the > g12a, which explains the significant line count in the g12a file. > > The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c: > > clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200) > > are available in the Git repository at: > > git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1 > > for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db: > > clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200) > > ---------------------------------------------------------------- Thanks. Pulled into clk-next
On Tue 11 Jun 2019 at 14:38, Jerome Brunet <jbrunet@baylibre.com> wrote: > Dear clock maintainers, > > Below is a request to pull Amlogic clock update for v5.3 based on the fixes > we just send. This update add the init() callback to the mpll clock driver > as discussed in the previous cycle. As promised, the rework to register/deregister > will follow. > > Apart from this, we've got a fairly regular update, adding a bunch of new > clocks to several SoC families. It also adds support for g12b derived from the > g12a, which explains the significant line count in the g12a file. > > The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c: > > clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200) > > are available in the Git repository at: > > git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1 > > for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db: > > clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200) > Hi Stephen, Could let us if you intend to take this PR as it is or if you are expecting any change ? Best regards Jerome
On Tue 25 Jun 2019 at 10:56, Jerome Brunet <jbrunet@baylibre.com> wrote: > On Tue 11 Jun 2019 at 14:38, Jerome Brunet <jbrunet@baylibre.com> wrote: > >> Dear clock maintainers, >> >> Below is a request to pull Amlogic clock update for v5.3 based on the fixes >> we just send. This update add the init() callback to the mpll clock driver >> as discussed in the previous cycle. As promised, the rework to register/deregister >> will follow. >> >> Apart from this, we've got a fairly regular update, adding a bunch of new >> clocks to several SoC families. It also adds support for g12b derived from the >> g12a, which explains the significant line count in the g12a file. >> >> The following changes since commit 3ff46efbcd90d3d469de8eddaf03d12293aaa50c: >> >> clk: meson: meson8b: fix a typo in the VPU parent names array variable (2019-05-20 12:11:08 +0200) >> >> are available in the Git repository at: >> >> git://github.com/BayLibre/clk-meson.git tags/clk-meson-5.3-1 >> >> for you to fetch changes up to eda91833f099277998814105c77b5b12cbfab6db: >> >> clk: meson: g12a: mark fclk_div3 as critical (2019-06-11 11:28:44 +0200) >> > > Hi Stephen, > > Could let us if you intend to take this PR as it is or if you are expecting > any change ? > > Best regards > Jerome Nevermind, I missed your reply. Thanks for merging. Regards