| Message ID | CAJZgTGF2ihuu_bSzQ93iBTf1YQ4_NM29S4iBFM8Fhd_RUaw2vQ@mail.gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | pinctrl: meson-gxl: fix GPIOX sdio pins | expand |
On Wed 05 Feb 2020 at 12:22, Nicolas Belin <nbelin@baylibre.com> wrote: > In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused > any issue so far because devices using these pins always take both pins > so the resulting configuration is OK. > > Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") > Signed-off-by: Nicolas Belin <nbelin@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> > --- > drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c > b/drivers/pinctrl/meson/pinctrl-meson-gxl.c > index 72c5373c8dc1..e8d1f3050487 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c > +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c > @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; > static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; > static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; > static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; > -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; > -static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; > +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; > +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; > static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; > > static const unsigned int nand_ce0_pins[] = { BOOT_8 };
Hi Nicolas, thanks for your patch! I can't apply it for some reason, something is weird with it... On Wed, Feb 5, 2020 at 12:22 PM Nicolas Belin <nbelin@baylibre.com> wrote: > @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; > static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; > static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; > static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; > -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; > -static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; > +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; > +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; > static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; > > static const unsigned int nand_ce0_pins[] = { BOOT_8 }; > -- For example the patch just ends here with -- two dashes. Please collect Jerome's ACK and resend using git-send-email if possible. Yours, Linus Walleij
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 72c5373c8dc1..e8d1f3050487 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; -static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; static const unsigned int nand_ce0_pins[] = { BOOT_8 };
In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused any issue so far because devices using these pins always take both pins so the resulting configuration is OK. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Signed-off-by: Nicolas Belin <nbelin@baylibre.com> --- drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --