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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YvudocI5ZABeT7xlTrESZBjgpi8XcmdIcFfkDQ2Fw4SVFih8TEmUJxkLwJuPbpON2doCkkjopTcN7UdfB2qvgYTsx2DZVVM1idWpdLp6N65I8y9E6+IiRyNzfMAVOq73q3xp40p3YIP6m4tryAnFsWgxDLAGDFlctgD9sVzk07MlVhxF25V08raqu6AA+mr474TOtfLakhSqqrg0x764pKNXteQsBYYz02AshSxabInU9e/I/9/tLVGqrEZ/f/yZl1bcVnH1IS47jrnydfAcxjPfxKsol7jIg7nlC+Rz/rbfb1vFDIut7Xq7JEAyojBWt1lmD483fcsSeor7wi66jEgCDIFkxtFsKDd2q0LDtCanjB+Hqt/DzOkvcceRYgFo2gQHliOjEvRj97GFKzbZHYUCYsK2TugsxwyB2toRjV7hZckNg7GTiaHS+4+/g2DFAQtVKISWlO35ozhUI5XxB8RYs1Rd9Uvqu5ayTlYJRNixhC98/wDOAjHBhebE+0E38fhx044CMF4v6YnhrTjVuzg6WNbnK+4bwOMwnoZrwhwdQdXQ+YDcOa1hpR8QFPqMkhuXW6/K2ki6OecmKqxQfF3jhlvj03m4sH5hdDBcCSULRGkKfw6iKnSmxp4xUiqtqTQyfXWcVjLQOx8PBRo1f9ZcvpuOQ7c2Fwwz9nynf7Cecvq0vbR7wznVvThPRV29ym4yT8AiOnChyGElCBo2Nsz3xKCpwrQjNvcl4R0l7AzG4ZvecE8xYiqcnH/aXQOH5gdWZC6UCM2y20QcuqbtYfTzpVSdDHXE/9CPLJhquO6KqSM6GWddMh3o2jsl7dt1WEbGryE2wQYv6ZHs6tT2fa60eP9txQTwLHTQwLVhjVSlSo8WBz9dkYF8Hm0t/1AoVtc43XNuh3HCJaRC2ze8B2dhiYr7oNLeKVgPC3gwH4okUi3E3DzR1MA33HMykFxKubm6DlzzWzRc7f68rVakD6k3+DaR4HMdt0VUlCkm0pa67C3kHdfWXM/2vZbGr105TE97pVuN9Lqw54J6isx/DevzvTq1GCwss2QnPlLYOK+wk7nrllYvhfXeWKMpDDfITompFju6d0pskZLVfvjBwhdQUzrXKYpc8BG4KKOdvkIP3InoFHENxwzEMS+/qam1yCxn+BGJnc4wxREjeRQow6NorUo6ZMI9hZG17lRt5++OlFlfsFfV/1m81SzyjTNZ//4YhtbR136yhazSLRJVNpbkXPlF/tjClrhvaWXXXK4kHfrr+swzGSjcIQ6pOd7wCtI/Ei/KFPypt+f/Ms6KVFackDekKTUOfiTOwmlpSerBQlAJHGk1S8qzM5Ysdbnk3hpdE3Zzg/5umnVPMRpqzkacRflk9ehmuEgbmD1/62I5CI65ThrRkKvGK2BERgW0CeB24ssP6Z5+5eQDNfPd9tS+aw6PBLkaA0OMCOuvnL1r+EoW4RgGckbsFxCGon0uhn6WQ1E3tpEPCWititrJp/fwnfiVuZcjJXhoxq5i+X3/02z1m6CyuJ6HcXjS44gdqSbOrVhM0IjtNHFUk/rGsEPOl3uq/y3FEEKzoSVFunU9cEOwfffTzMTw+tcSwr4L X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3486b4cc-aea9-450b-c987-08dbf5c674d9 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2023 19:14:51.6940 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DuUV5C49CAmhglNAiptmgrB1Gqiuty0gy71ud33tZ7ng9nOFOW0VSKsetve70xi/ X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6051 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231205_111500_487958_378B6FA7 X-CRM114-Status: GOOD ( 17.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SMMUv3 driver was originally written in 2015 when the iommu driver facing API looked quite different. The API has evolved, especially lately, and the driver has fallen behind. This work aims to bring make the SMMUv3 driver the best IOMMU driver with the most comprehensive implementation of the API. After all parts it addresses: - Global static BLOCKED and IDENTITY domains with 'never fail' attach semantics. BLOCKED is desired for efficient VFIO. - Support map before attach for PAGING iommu_domains. - attach_dev failure does not change the HW configuration. - Fully hitless transitions between IDENTITY -> DMA -> IDENTITY. The API has IOMMU_RESV_DIRECT which is expected to be continuously translating. - Safe transitions between PAGING -> BLOCKED, do not ever temporarily do IDENTITY. This is required for iommufd security. - Full PASID API support including: - S1/SVA domains attached to PASIDs - IDENTITY/BLOCKED/S1 attached to RID - Change of the RID domain while PASIDs are attached - Streamlined SVA support using the core infrastructure - Hitless, whenever possible, change between two domains - iommufd IOMMU_GET_HW_INFO, IOMMU_HWPT_ALLOC_NEST_PARENT, and IOMMU_DOMAIN_NESTED support Over all these things are going to become more accessible to iommufd, and exposed to VMs, so it is important for the driver to have a robust implementation of the API. The work is split into three parts, with this part largely focusing on the STE and building up to the BLOCKED & IDENTITY global static domains. The second part largely focuses on the CD and builds up to having a common PASID infrastructure that SVA and S1 domains equally use. The third part has some random cleanups and the iommufd related parts. Overall this takes the approach of turning the STE/CD programming upside down where the CD/STE value is computed right at a driver callback function and then pushed down into programming logic. The programming logic hides the details of the required CD/STE tear-less update. This makes the CD/STE functions independent of the arm_smmu_domain which makes it fairly straightforward to untangle all the different call chains, and add news ones. Further, this frees the arm_smmu_domain related logic from keeping track of what state the STE/CD is currently in so it can carefully sequence the correct update. There are many new update pairs that are subtly introduced as the work progresses. The locking to support BTM via arm_smmu_asid_lock is a bit subtle right now and patches throughout this work adjust and tighten this so that it is clearer and doesn't get broken. Once the lower STE layers no longer need to touch arm_smmu_domain we can isolate struct arm_smmu_domain to be only used for PAGING domains, audit all the to_smmu_domain() calls to be only in PAGING domain ops, and introduce the normal global static BLOCKED/IDENTITY domains using the new STE infrastructure. Part 2 will ultimately migrate SVA over to use arm_smmu_domain as well. All parts are on github: https://github.com/jgunthorpe/linux/commits/smmuv3_newapi v3: - Use some local variables in arm_smmu_get_step_for_sid() for clarity - White space and spelling changes - Commit message updates - Keep master->domain_head initialized to avoid a list_del corruption v2: https://lore.kernel.org/r/0-v2-de8b10590bf5+400-smmuv3_newapi_p1_jgg@nvidia.com - Rebased on v6.7-rc1 - Improve the comment for arm_smmu_write_entry_step() - Fix the botched memcmp - Document the spec justification for the SHCFG exclusion in used - Include STRTAB_STE_1_SHCFG for STRTAB_STE_0_CFG_S2_TRANS in used - WARN_ON for unknown STEs in used - Fix error unwind in arm_smmu_attach_dev() - Whitespace, spelling, and checkpatch related items v1: https://lore.kernel.org/r/0-v1-e289ca9121be+2be-smmuv3_newapi_p1_jgg@nvidia.com Jason Gunthorpe (19): iommu/arm-smmu-v3: Add a type for the STE iommu/arm-smmu-v3: Master cannot be NULL in arm_smmu_write_strtab_ent() iommu/arm-smmu-v3: Remove ARM_SMMU_DOMAIN_NESTED iommu/arm-smmu-v3: Make STE programming independent of the callers iommu/arm-smmu-v3: Consolidate the STE generation for abort/bypass iommu/arm-smmu-v3: Move arm_smmu_rmr_install_bypass_ste() iommu/arm-smmu-v3: Move the STE generation for S1 and S2 domains into functions iommu/arm-smmu-v3: Build the whole STE in arm_smmu_make_s2_domain_ste() iommu/arm-smmu-v3: Hold arm_smmu_asid_lock during all of attach_dev iommu/arm-smmu-v3: Compute the STE only once for each master iommu/arm-smmu-v3: Do not change the STE twice during arm_smmu_attach_dev() iommu/arm-smmu-v3: Put writing the context descriptor in the right order iommu/arm-smmu-v3: Pass smmu_domain to arm_enable/disable_ats() iommu/arm-smmu-v3: Remove arm_smmu_master->domain iommu/arm-smmu-v3: Add a global static IDENTITY domain iommu/arm-smmu-v3: Add a global static BLOCKED domain iommu/arm-smmu-v3: Use the identity/blocked domain during release iommu/arm-smmu-v3: Pass arm_smmu_domain and arm_smmu_device to finalize iommu/arm-smmu-v3: Convert to domain_alloc_paging() drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 729 +++++++++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 12 +- 2 files changed, 477 insertions(+), 264 deletions(-) base-commit: ca7fcaff577c92d85f0e05cc7be79759155fe328 Tested-by: Moritz Fischer