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From there the focus is on building out the core infrastructure for dealing with PASID and CD entries, then keeping track of unique SSID's for ATS invalidation. The ATS ordering is generalized so that the PASID flow can use it and put into a form where it is fully hitless, whenever possible. Care is taken to ensure that ATC flushes are present after any change in translation. Finally we simply kill the entire outdated SVA mmu_notifier implementation in one shot and switch it over to the newly created generic PASID & CD code. This avoids the messy and confusing approach of trying to incrementally untangle this in place. The new code is small and simple enough this is much better than trying to figure out smaller steps. Once SVA is resting on the right CD code it is straightforward to make the PASID interface functionally complete. It achieves the same goals as the several series from Michael and the S1DSS series from Nicolin that were trying to improve portions of the API. This is on github: https://github.com/jgunthorpe/linux/commits/smmuv3_newapi v7: - Second half of the split series - Rebase on Joerg's latest - Accommodate ARM_SMMU_FEAT_ATTR_TYPES_OVR for the S1DSS code - Include the S1DSS kunit tests - Include hunks to adjust the unit tests to API changes from this series - Move 3 BTM related patches out of this series, they can go in the BTM enablement series. - Move the domain_alloc_sva() conversion to the first patch, and rebase on the accepted core code change - Use the new core APIs for the PASID ops - Revise commit messages v6: https://lore.kernel.org/r/0-v6-228e7adf25eb+4155-smmuv3_newapi_p2_jgg@nvidia.com Jason Gunthorpe (14): iommu/arm-smmu-v3: Convert to domain_alloc_sva() iommu/arm-smmu-v3: Start building a generic PASID layer iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list iommu/arm-smmu-v3: Make changing domains be hitless for ATS iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain iommu/arm-smmu-v3: Do not use master->sva_enable to restrict attaches iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*() interface iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used iommu/arm-smmu-v3: Test the STE S1DSS functionality iommu/arm-smmu-v3: Allow a PASID to be set when RID is IDENTITY/BLOCKED iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 434 +++----------- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 116 +++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 534 +++++++++++++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 52 +- 4 files changed, 645 insertions(+), 491 deletions(-) base-commit: 6bbed5b0a211d926fe494b722f5198a82f58a5c9 Tested-by: Nicolin Chen