[0/6] PMUv3 event handling improvements

Message

Will Deacon Oct. 10, 2018, 4:31 p.m. UTC

Hi all,

Following on-list discussion with Ganapat [1], I found and fixed a few
issues with the arm64 PMUv3 code:

  - We don't reject standalone CHAIN events requested in a 32-bit perf event
  - We don't interpret the upper 32 bits of the PMCEID registers for 8.1 events
  - We have duplicate cache events for read and write, which is very confusing
  - Our events are straddled between arm_pmu.c and arm_pmu.h and aren't in
    numerical order
  - We don't advertise a bunch fo new events that have been added since v8.0

This series addresses all of these problems.

Cheers,

Will

[1] http://lkml.kernel.org/r/CAKTKpr6SQUc9EgdYL2N32a=[e-mail]

--->8

Will Deacon (6):
  arm64: perf: Reject stand-alone CHAIN events for PMUv3
  arm64: perf: Terminate PMU assignment statements with semicolons
  arm64: perf: Add support for Armv8.1 PMCEID register format
  arm64: perf: Remove duplicate generic cache events
  arm64: perf: Move event definitions into perf_event.h
  arm64: perf: Hook up new events

 arch/arm64/include/asm/perf_event.h | 164 ++++++++++++++++++++++++--
 arch/arm64/kernel/perf_event.c      | 225 ++++++++++--------------------------
 drivers/perf/arm_pmu.c              |   8 +-
 include/linux/perf/arm_pmu.h        |   5 +-
 4 files changed, 225 insertions(+), 177 deletions(-)