From patchwork Wed Oct 10 16:31:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 10634829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF710679F for ; Wed, 10 Oct 2018 16:33:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1CE262A9DE for ; Wed, 10 Oct 2018 16:33:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1B1C72AAEC; Wed, 10 Oct 2018 16:33:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8CDAF2A9DE for ; Wed, 10 Oct 2018 16:33:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=4ezsRo4xjkHujyaXLPn7AAtGs59ka8M0qicOVln6jaA=; b=Bnx 2afeOSZWHyWH4lnl4tC4iSierVmHorxYfUkd3/coj26VM10H1YKKo91RIRBRUBxftEK3BwLijcsxW ErWiQWcESt80YCH8gXMIQDqv6ip5GOz0kS+/lNr5ez9co1a8EQ+n9lIarkEDx7EqZdoUnvJZWiIvG 28q9KvyGl+/XT8ol5nWFbg+tOaNYsftE+PPV0hH9mnHaYWI5UJLNa0KnvAoJdpjyM+edff3e7ySZ+ nrWWTgXDLNr2WY1AJ6saNkZ1eugnL82r4mcOapoWLmAUHxhXB3Bp6tluOCLWDXtb3Vzy5Rf4mxfFl Kt4j5jUh9JHuuTFooa1a9/mzhoCfkbQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gAHPj-0002N7-LD; Wed, 10 Oct 2018 16:32:47 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gAHP5-00023s-Gf for linux-arm-kernel@lists.infradead.org; Wed, 10 Oct 2018 16:32:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 43E9A1596; Wed, 10 Oct 2018 09:31:57 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 12DC33F5B3; Wed, 10 Oct 2018 09:31:57 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id C0D121AE088A; Wed, 10 Oct 2018 17:31:56 +0100 (BST) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/6] PMUv3 event handling improvements Date: Wed, 10 Oct 2018 17:31:49 +0100 Message-Id: <1539189115-16221-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181010_093207_592955_2A08DF0C X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Ganapatrao.Kulkarni@cavium.com, Will Deacon , suzuki.poulose@arm.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi all, Following on-list discussion with Ganapat [1], I found and fixed a few issues with the arm64 PMUv3 code: - We don't reject standalone CHAIN events requested in a 32-bit perf event - We don't interpret the upper 32 bits of the PMCEID registers for 8.1 events - We have duplicate cache events for read and write, which is very confusing - Our events are straddled between arm_pmu.c and arm_pmu.h and aren't in numerical order - We don't advertise a bunch fo new events that have been added since v8.0 This series addresses all of these problems. Cheers, Will [1] http://lkml.kernel.org/r/CAKTKpr6SQUc9EgdYL2N32a=szUmSs82Mbb4y89htbVQhTPp2rQ@mail.gmail.com --->8 Will Deacon (6): arm64: perf: Reject stand-alone CHAIN events for PMUv3 arm64: perf: Terminate PMU assignment statements with semicolons arm64: perf: Add support for Armv8.1 PMCEID register format arm64: perf: Remove duplicate generic cache events arm64: perf: Move event definitions into perf_event.h arm64: perf: Hook up new events arch/arm64/include/asm/perf_event.h | 164 ++++++++++++++++++++++++-- arch/arm64/kernel/perf_event.c | 225 ++++++++++-------------------------- drivers/perf/arm_pmu.c | 8 +- include/linux/perf/arm_pmu.h | 5 +- 4 files changed, 225 insertions(+), 177 deletions(-)