From patchwork Tue Nov 27 12:41:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 10700359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5551513BF for ; Tue, 27 Nov 2018 12:41:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 443662B07F for ; Tue, 27 Nov 2018 12:41:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 37D772B07B; Tue, 27 Nov 2018 12:41:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D8D9F2B02F for ; Tue, 27 Nov 2018 12:41:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=j/06EUBicHT/vBMTdINsB2vLYNlw7VxoBhFoISKW82s=; b=uI5 ofI2OyqMDVwRrlXhJwU2j7iTfQwSdtBeVMCsQ7h/XR2OfMY01nAWBWlpxfFHKeAD2pGN+lAYpqhJc TdJEYygyXiATD8bhJ5kIKwL0swr01HT6ufkkM3UKdMxAiert51Q5HUnsjnpRe6SIydr+I+skBfE1g Nt3k3ZK/VvZYA0TUETdGI0ehVPy4+Oij9WN+LBGLiJhezJH/+bv5TI+2tqFC6uA4tjEU+bLMS3CGp uCsTrkeVVrSVYnPhJOlVSMFRhbzvfq9eb+Yq0vz9GiYnh8SAemKos7LoPrhP1qVdpwQwjEVW4yCxE eFDFlvkyfW1c1gvGzg1Ofv9YVz/yFXA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRcge-0006wk-Q7; Tue, 27 Nov 2018 12:41:56 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRcgb-0006va-LH for linux-arm-kernel@lists.infradead.org; Tue, 27 Nov 2018 12:41:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3271C35FA; Tue, 27 Nov 2018 04:41:41 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EB5383F575; Tue, 27 Nov 2018 04:41:40 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id AE3251AE0C3D; Tue, 27 Nov 2018 12:41:58 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/3] arm64: Add support for speculation barrier instruction (SB) Date: Tue, 27 Nov 2018 12:41:54 +0000 Message-Id: <1543322517-470-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181127_044153_735728_8A9CD160 X-CRM114-Status: GOOD ( 11.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, catalin.marinas@arm.com, Will Deacon , suzuki.poulose@arm.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi all, As part of the fallout from specdown and meltre, Armv8.5 introduces an architected Speculation Barrier (SB) instruction. Unlike CSDB, this is not retrofitted to existing CPUs, so we need to plumb in an HWCAP and make use of the alternatives framework to patch it over our current DSB; ISB sequence on CPUs that support it. Cheers, Will --->8 Will Deacon (3): arm64: Add support for SB barrier and patch in over DSB; ISB sequences arm64: entry: Place an SB sequence following an ERET instruction arm64: entry: Remove confusing comment arch/arm64/include/asm/assembler.h | 13 +++++++++++++ arch/arm64/include/asm/barrier.h | 4 ++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/sysreg.h | 6 ++++++ arch/arm64/include/asm/uaccess.h | 3 +-- arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 12 ++++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kernel/entry.S | 6 ++---- arch/arm64/kvm/hyp/entry.S | 1 + arch/arm64/kvm/hyp/hyp-entry.S | 4 ++++ 11 files changed, 47 insertions(+), 7 deletions(-)