From patchwork Tue Nov 27 19:44:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 10701341 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 39F0B13AD for ; Tue, 27 Nov 2018 19:45:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 285302C334 for ; Tue, 27 Nov 2018 19:45:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C2602C34E; Tue, 27 Nov 2018 19:45:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C8D102C334 for ; Tue, 27 Nov 2018 19:45:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=hAdKn5bv0cnsz1o9sWblfNG7/VuzEAA3KPgsZQaxOhM=; b=ACk FnJutQxny6iMuzZktgaqQ3D88PZMpWJqxtsIH9lD9dO1iD4QNR5qKL0iPml2rsaKS+B2ppBe+szBM wKg/ray2tdfaXTdn42pVMYjoqBKe1LMAC2cUtUQThnVjYPIiaXJvGh3kJi6ZyNyo7lo8eGoOZP3Tg b+DGIshpUYQTtiNZra3d75nLngaxCoyQ+SlKkWRyM8XxzCGY0VO1bt5DIbFZh50o5RJYuHilZkdvd w+VKuOH8hWduPvbUuwJE3UpUR7gRA3WNvd7mFlvsFXGBhzsbnskKYGcTI2XdUZmc9qPVxEQuVIa/S DKbwPWwccdl2Ry3ZGvVY8/wa2+ribCw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRjI3-0005nO-Pv; Tue, 27 Nov 2018 19:44:59 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRjHw-0005XL-Jn for linux-arm-kernel@lists.infradead.org; Tue, 27 Nov 2018 19:44:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5861B32E5; Tue, 27 Nov 2018 11:44:42 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 28ED23F575; Tue, 27 Nov 2018 11:44:42 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 091461AE0A0D; Tue, 27 Nov 2018 19:44:59 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/4] Rewrite of percpu atomics and introduction of LSE Date: Tue, 27 Nov 2018 19:44:43 +0000 Message-Id: <1543347887-21101-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181127_114452_662234_B88153F5 X-CRM114-Status: UNSURE ( 9.46 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: catalin.marinas@arm.com, Will Deacon , ard.biesheuvel@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi all, Whilst looking at what it would take to use LSE atomics for the percpu operations, I ended up rewriting most of our implementation to address a number of issues I spotted. The result is a net reduction of code, whilst at the same time avoiding duplication, adding support for LSE and improving our manipulation of the preempt count. Ard -- I think most of this is orthogonal to your LSE work, since this doesn't make use of the out-of-line atomics at all. Still, please take a look all the same! Cheers, Will --->8 Will Deacon (4): arm64: Avoid redundant type conversions in xchg() and cmpxchg() arm64: Avoid masking "old" for LSE cmpxchg() implementation arm64: percpu: Rewrite per-cpu ops to allow use of LSE atomics arm64: cmpxchg: Use "K" instead of "L" for ll/sc immediate constraint arch/arm64/include/asm/atomic_ll_sc.h | 63 +++--- arch/arm64/include/asm/atomic_lse.h | 48 ++--- arch/arm64/include/asm/cmpxchg.h | 116 +++++----- arch/arm64/include/asm/percpu.h | 390 ++++++++++++++-------------------- 4 files changed, 278 insertions(+), 339 deletions(-)