From patchwork Fri Mar 22 16:23:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Thierry X-Patchwork-Id: 10866221 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7CC211390 for ; Fri, 22 Mar 2019 16:24:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C7A429743 for ; Fri, 22 Mar 2019 16:24:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 50C88297A8; Fri, 22 Mar 2019 16:24:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E0ED529743 for ; Fri, 22 Mar 2019 16:24:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=C/Td6Yudw3sE9WJStqSvSnte7KRauNziVEJrPLaLoXc=; b=B8P 1XG49oqRt7ebQfvq3eUKH118G2K3XGDL1tDs7bPo8Cy+j+Nf1zSyX8y89urRVlu3Jp+SlKe0JsLzh qk6TUB2QHTshyvQIE4HhqQ1XT49XOdBMbRFHJ266EeiuGUWEHIX4a7ucBuZ2p69MKudri/SyRwEbC ok3e7orBxuTe0j/oVfDQGqVuyarII7Fv9YnLd278v2AN3hLdUhoFxFU+nkIp460qiz8A/8fRFrLDO b6bkfi07Z9Z0ua70KOUSrZVFhi9YAtBx9YPSMBqXfIhr9s4PbGyyAClMHf7NDmQzTq/DTNO1jkXfe JneTpdpHesVgYX2mvSzkM5d8wRNpJgQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h7My0-0001xd-Lx; Fri, 22 Mar 2019 16:24:24 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h7Mxq-0001nh-1r for linux-arm-kernel@lists.infradead.org; Fri, 22 Mar 2019 16:24:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0364A78; Fri, 22 Mar 2019 09:24:11 -0700 (PDT) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D43023F59C; Fri, 22 Mar 2019 09:24:09 -0700 (PDT) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 0/9] arm_pmu: Use NMI for perf interrupt Date: Fri, 22 Mar 2019 16:23:55 +0000 Message-Id: <1553271844-49003-1-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190322_092414_109599_1F501404 X-CRM114-Status: GOOD ( 14.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Julien Thierry , peterz@infradead.org, will.deacon@arm.com, acme@kernel.org, alexander.shishkin@linux.intel.com, mingo@redhat.com, namhyung@kernel.org, jolsa@redhat.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, On arm64, perf reports that counter overflow very often (too often) happen in function that potentially enabled interrutps: $ perf record -a -- sleep 60; perf report -F overhead,symbol [...] # Overhead Symbol # ........ .......................................... # 6.58% [k] _raw_spin_unlock_irq 6.10% [k] _raw_spin_unlock_irqrestore 5.52% [k] ___bpf_prog_run 4.37% [k] el0_svc_common 2.58% [k] arch_cpu_idle 2.39% [k] kmem_cache_alloc 2.06% [k] __seccomp_filter [...] The root issue is, if an overflow happens while executing with interrupts disabled, the perf event will only be handled when interrupts are reenabled (i.e. when the PMU interrupt is taken). The result being the event being reported at the interrupt enabling location rather than where the overflow actually happened. Now that we have support for pseudo-NMI on arm64 with GICv3, we can use it to improve the profiling done using the PMU interrupt. With these changes, on the same machine, we get: # Overhead Symbol # ........ .................................. # 7.06% [k] ___bpf_prog_run 4.08% [k] __update_load_avg_se 4.02% [k] ktime_get_ts64 3.77% [k] __ll_sc_arch_atomic_add_return 3.71% [k] file_ra_state_init 3.62% [k] __ll_sc_arch_atomic64_sub 3.53% [k] __ll_sc___cmpxchg_case_acq_32 [...] _raw_spin_unlock_irq/irqrestore don't event appear anymore in the perf trace. * Patches 1 to 4 remove the need to use spinlocks for the Arm PMU driver for Armv7 and Armv8 (aarch64). * Patches 5 moves the locking to Armv6 specific code which is the sole user * Patches 6 and 7 make the PMU interrupt handler NMI-safe * Patches 8 and 9 enable using pseudo-NMI for the PMU interrupt when the feature is available Changes since v1[1]: - Rebased on v5.1-rc1 - Pseudo-NMI has changed a lot since then, use the (now merged) NMI API - Remove locking from armv7 perf_event - Use locking only in armv6 perf_event - Use direct counter/type registers insted of selector register for armv8 [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/554611.html Cheers, Julien --> Julien Thierry (8): arm64: perf: Remove PMU locking arm: perf: save/resore pmsel arm: perf: Remove Remove PMU locking perf/arm_pmu: Move PMU lock to ARMv6 events arm64: perf: Do not call irq_work_run in NMI context arm/arm64: kvm: pmu: Make overflow handler NMI safe arm_pmu: Introduce pmu_irq_ops arm_pmu: Use NMIs for PMU Mark Rutland (1): arm64: perf: avoid PMXEV* indirection arch/arm/kernel/perf_event_v6.c | 26 +++++--- arch/arm/kernel/perf_event_v7.c | 77 +++++++--------------- arch/arm64/kernel/perf_event.c | 122 ++++++++++++++++++++++------------ drivers/perf/arm_pmu.c | 143 ++++++++++++++++++++++++++++++++++------ include/kvm/arm_pmu.h | 1 + include/linux/perf/arm_pmu.h | 5 -- virt/kvm/arm/pmu.c | 37 +++++++++-- 7 files changed, 277 insertions(+), 134 deletions(-) --- 1.9.1