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Wysocki" , Lorenzo Pieralisi , Fabio Estevam , Lucas Stach , Aisheng Dong Subject: [RFC 0/7] cpuidle: Add poking mechanism to support non-IPI wakeup Thread-Topic: [RFC 0/7] cpuidle: Add poking mechanism to support non-IPI wakeup Thread-Index: AQHU5J/uL6RBBX3AA0GxPKCBIrMc4A== Date: Wed, 27 Mar 2019 13:21:05 +0000 Message-ID: <1553692845-20983-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0701CA0038.eurprd07.prod.outlook.com (2603:10a6:800:90::24) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [212.146.100.6] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5a5bd5ea-8e37-42a4-f439-08d6b2b710e8 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB6051; x-ms-traffictypediagnostic: AM0PR04MB6051: x-ms-exchange-purlcount: 1 x-microsoft-antispam-prvs: x-forefront-prvs: 0989A7979C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(136003)(39860400002)(396003)(346002)(376002)(199004)(189003)(25786009)(14444005)(68736007)(4326008)(6436002)(5660300002)(6116002)(71200400001)(71190400001)(3846002)(256004)(8936002)(8676002)(6636002)(2501003)(66066001)(305945005)(2906002)(53936002)(81156014)(6512007)(7736002)(81166006)(7416002)(97736004)(6486002)(36756003)(54906003)(6306002)(44832011)(50226002)(486006)(106356001)(6506007)(386003)(186003)(110136005)(102836004)(966005)(14454004)(476003)(86362001)(99286004)(52116002)(478600001)(316002)(2616005)(26005)(105586002)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB6051; H:AM0PR04MB5779.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: xfNChds0TnW/8KAmZfUTn60p4tg5NdXtUJGJevvC5OAK2sF7p7MrbS6ZAA+bUeISCbMSZDkKd8+Lfhv5zXMizqYf9hZNIfIS+ktey9+cl/8YIeUr7xjKEGmklOPfKhkTxLdY3Bl1X/fXPUZZQJZtcVccmAfPRPFxgdGMKvwBr9lit8KODC6C4KFqSTNzYKKfuZX5YgjHYLhALfXsB4cvYGEkt+O+Ftp1uhCD7dv4/0+qq/2msuF6Zl2/tWkaLU4jMv+hZTG5GZd/BjiFNUUwUfYILmuDBTbpGmZ9qZnCfur4KIu8SoqZzymVSIZFrzmRWzhlvlTlyf00RLQ2bsBMLHohHG36ZPxZoLZLuM2pMbUcZPuioofR7WDYcLCiS+09WvVmk14qXfBlD8GSAHaPahswIX+/bi9++M9w0z3bcSA= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5a5bd5ea-8e37-42a4-f439-08d6b2b710e8 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2019 13:21:05.4897 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6051 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190327_062110_956074_043057C8 X-CRM114-Status: GOOD ( 12.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , "linux-pm@vger.kernel.org" , dl-linux-imx , "linux-arm-kernel@lists.infradead.org" , Linux Kernel Mailing List Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This work is a workaround I'm looking into (more as a background task) in order to add support for cpuidle on i.MX8MQ based platforms. The main idea here is getting around the missing GIC wake_request signal (due to integration design issue) by waking up a each individual core through some dedicated SW power-up bits inside the power controller (GPC) right before every IPI is requested for that each individual core. This work is basically composed of four parts (in kernel): - the cpuidle core poking mechanism along with the related sched/irq_work calls - the cpuidle-arm ops addition in order to support poking, along with the 'local-wakeup-poke' DT idle state knob - the psci and cpu_ops cpu_poke addition - the i.MX8MQ specific idle states in dts There is also a change needed in TF-A which is available here: https://lists.trustedfirmware.org/pipermail/tf-a/2019-March/000009.html Abel Vesa (7): sched: idle: Add sched get idle state helper cpuidle: Add cpu poke support smp: Poke the cores before requesting IPI psci: Add cpu_poke ops to support core poking cpuidle-arm: Add ops to support poke alonside enter cpuidle-arm: Add arm64 wake helper for cpu_poke op arm64: dts: imx8mq: Add cpu-sleep state with poke wake-up enabled arch/arm64/boot/dts/freescale/imx8mq.dtsi | 20 ++++++++++++++++++ arch/arm64/include/asm/cpu_ops.h | 1 + arch/arm64/include/asm/cpuidle.h | 6 ++++++ arch/arm64/kernel/cpuidle.c | 8 ++++++++ arch/arm64/kernel/psci.c | 1 + drivers/cpuidle/cpuidle-arm.c | 13 +++++++++++- drivers/cpuidle/cpuidle.c | 34 +++++++++++++++++++++++++++++++ drivers/cpuidle/dt_idle_states.c | 15 +++++++++----- drivers/cpuidle/dt_idle_states.h | 10 +++++++++ drivers/firmware/psci.c | 6 ++++++ include/linux/cpuidle.h | 7 +++++++ include/linux/psci.h | 1 + include/uapi/linux/psci.h | 2 ++ kernel/irq_work.c | 19 ++++++++++++++--- kernel/sched/core.c | 16 ++++++++++----- kernel/sched/idle.c | 11 ++++++++++ kernel/smp.c | 10 ++++++++- kernel/time/tick-broadcast.c | 4 ++++ 18 files changed, 169 insertions(+), 15 deletions(-)