From patchwork Thu Apr 25 09:17:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 10916361 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 23FD714DB for ; Thu, 25 Apr 2019 09:17:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 121C828BB7 for ; Thu, 25 Apr 2019 09:17:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 047EE28C2B; Thu, 25 Apr 2019 09:17:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A15E528BB7 for ; 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Thu, 25 Apr 2019 11:17:30 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0018838; Thu, 25 Apr 2019 09:17:29 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BC2851615; Thu, 25 Apr 2019 09:17:29 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:29 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:28 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , Subject: [PATCH v2 0/6] hwspinlock: allow sharing of hwspinlocks Date: Thu, 25 Apr 2019 11:17:17 +0200 Message-ID: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-25_08:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_021741_070495_CAB0F264 X-CRM114-Status: GOOD ( 17.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Benjamin Gaignard , Fabien Dessenne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The current implementation does not allow two different devices to use a common hwspinlock. This patch set proposes to have, as an option, some hwspinlocks shared between several users. Below is an example that explain the need for this: exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000d000 0x400>; hwlocks = <&hsem 1>; }; The two drivers (stm32mp1-exti and syscon) refer to the same hwlock. With the current hwspinlock implementation, only the first driver succeeds in requesting (hwspin_lock_request_specific) the hwlock. The second request fails. The proposed approach does not modify the API, but extends the DT 'hwlocks' property with a second optional parameter (the first one identifies an hwlock) that specifies whether an hwlock is requested for exclusive usage (current behavior) or can be shared between several users. Examples: hwlocks = <&hsem 8>; Ref to hwlock #8 for exclusive usage hwlocks = <&hsem 8 0>; Ref to hwlock #8 for exclusive (0) usage hwlocks = <&hsem 8 1>; Ref to hwlock #8 for shared (1) usage As a constraint, the #hwlock-cells value must be 1 or 2. In the current implementation, this can have theorically any value but: - all of the exisiting drivers use the same value : 1. - the framework supports only one value : 1 (see implementation of of_hwspin_lock_simple_xlate()) Hence, it shall not be a problem to restrict this value to 1 or 2 since it won't break any driver. Changes since v1: * Removed useless 'status = "okay"' from stm32mp157c.dtsi Fabien Dessenne (6): dt-bindings: hwlock: add support of shared locks hwspinlock: allow sharing of hwspinlocks dt-bindings: hwlock: update STM32 #hwlock-cells value ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC ARM: dts: stm32: Add hwlock for irqchip on stm32mp157 ARM: dts: stm32: hwlocks for GPIO for stm32mp157 .../devicetree/bindings/hwlock/hwlock.txt | 27 +++++-- .../bindings/hwlock/st,stm32-hwspinlock.txt | 6 +- Documentation/hwspinlock.txt | 10 ++- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 2 + arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++ drivers/hwspinlock/hwspinlock_core.c | 82 +++++++++++++++++----- drivers/hwspinlock/hwspinlock_internal.h | 2 + 7 files changed, 107 insertions(+), 31 deletions(-)