| Message ID | 1589218356-17475-1-git-send-email-yibin.gong@nxp.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | add ecspi ERR009165 for i.mx6/7 soc family | expand |
On Tue, May 12, 2020 at 01:32:23AM +0800, Robin Gong wrote: > There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO > transfer to be send twice in DMA mode. Please get more information from: > https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding > new sdma ram script which works in XCH mode as PIO inside sdma instead > of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be > exist on all legacy i.mx6/7 soc family before i.mx6ul. > NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/ > 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips > still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi' > for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata > or not. > The first two reverted patches should be the same issue, though, it > seems 'fixed' by changing to other shp script. Hope Sean or Sascha could > have the chance to test this patch set if could fix their issues. > Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work > on i.mx8mm because the event id is zero. It's not nice to break SPI support when the new firmware is not present and I think we can do better. Wouldn't it be possible to fall back to PIO in this case? Sascha
On 2020/05/13 Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Tue, May 12, 2020 at 01:32:23AM +0800, Robin Gong wrote: > > There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO > > transfer to be send twice in DMA mode. Please get more information from: > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww. > > > nxp.com%2Fdocs%2Fen%2Ferrata%2FIMX6DQCE.pdf&data=02%7C01%7C > yibin.g > > > ong%40nxp.com%7C4276d42955334886056508d7f70e18af%7C686ea1d3bc2b4 > c6fa92 > > > cd99c5c301635%7C0%7C1%7C637249512224944620&sdata=vh0e3BER01 > 02648t9HRe14h%2BaE9m%2BAlJ5Smd6v%2B9AhM%3D&reserved=0. The > workaround is adding new sdma ram script which works in XCH mode as PIO > inside sdma instead of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. > The issue should be exist on all legacy i.mx6/7 soc family before i.mx6ul. > > NXP fix this design issue from i.mx6ul, so newer chips including > > i.mx6ul/ 6ull/6sll do not need this workaroud anymore. All other > > i.mx6/7/8 chips still need this workaroud. This patch set add new > 'fsl,imx6ul-ecspi' > > for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need > > errata or not. > > The first two reverted patches should be the same issue, though, it > > seems 'fixed' by changing to other shp script. Hope Sean or Sascha > > could have the chance to test this patch set if could fix their issues. > > Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work > > on i.mx8mm because the event id is zero. > > It's not nice to break SPI support when the new firmware is not present and I > think we can do better. Wouldn't it be possible to fall back to PIO in this case? I'm afraid that's not easy since spi driver don't know which firmware used. Could I add some comments in commit log?
There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO transfer to be send twice in DMA mode. Please get more information from: https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding new sdma ram script which works in XCH mode as PIO inside sdma instead of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be exist on all legacy i.mx6/7 soc family before i.mx6ul. NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/ 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi' for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata or not. The first two reverted patches should be the same issue, though, it seems 'fixed' by changing to other shp script. Hope Sean or Sascha could have the chance to test this patch set if could fix their issues. Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work on i.mx8mm because the event id is zero. PS: Please get sdma firmware from below linux-firmware and copy it to your local rootfs /lib/firmware/imx/sdma. https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma v2: 1.Add commit log for reverted patches. 2.Add comment for 'ecspi_fixed' in sdma driver. 3.Add 'fsl,imx6sll-ecspi' compatible instead of 'fsl,imx6ul-ecspi' rather than remove. v3: 1.Confirm with design team make sure ERR009165 fixed on i.mx6ul/i.mx6ull /i.mx6sll, not fixed on i.mx8m/8mm and other i.mx6/7 legacy chips. Correct dts related dts patch in v2. 2.Clean eratta information in binding doc and new 'tx_glitch_fixed' flag in spi-imx driver to state ERR009165 fixed or not. 3.Enlarge burst size to fifo size for tx since tx_wml set to 0 in the errata workaroud, thus improve performance as possible. v4: 1.Add Ack tag from Mark and Vinod 2.Remove checking 'event_id1' zero as 'event_id0'. v5: 1.Add the last patch for compatible with the current uart driver which using rom script, so both uart ram script and rom script supported in latest firmware, by default uart rom script used. UART driver will be broken without this patch. v6: 1.Resend after rebase the latest next branch. 2.Remove below No.13~No.15 patches of v5 because they were mergered. ARM: dts: imx6ul: add dma support on ecspi ARM: dts: imx6sll: correct sdma compatible arm64: defconfig: Enable SDMA on i.mx8mq/8mm 3.Revert "dmaengine: imx-sdma: fix context cache" since 'context_loaded' removed. v7: 1.Put the last patch 13/13 'Revert "dmaengine: imx-sdma: fix context cache"' to the ahead of 03/13 'Revert "dmaengine: imx-sdma: refine to load context only once" so that no building waring during comes out during bisect. 2.Address Sascha's comments, including eliminating any i.mx6sx in this series, adding new 'is_imx6ul_ecspi()' instead imx in imx51 and taking care SMC bit for PIO. 3.Add back missing 'Reviewed-by' tag on 08/15(v5):09/13(v7) 'spi: imx: add new i.mx6ul compatible name in binding doc' Robin Gong (13): Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core" Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores" Revert "dmaengine: imx-sdma: fix context cache" Revert "dmaengine: imx-sdma: refine to load context only once" dmaengine: imx-sdma: remove dupilicated sdma_load_context dmaengine: imx-sdma: add mcu_2_ecspi script spi: imx: fix ERR009165 spi: imx: remove ERR009165 workaround on i.mx6ul spi: imx: add new i.mx6ul compatible name in binding doc dmaengine: imx-sdma: remove ERR009165 on i.mx6ul dma: imx-sdma: add i.mx6ul compatible name dmaengine: imx-sdma: fix ecspi1 rx dma not work on i.mx8mm dmaengine: imx-sdma: add uart rom script .../devicetree/bindings/dma/fsl-imx-sdma.txt | 1 + .../devicetree/bindings/spi/fsl-imx-cspi.txt | 1 + arch/arm/boot/dts/imx6q.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 8 +-- drivers/dma/imx-sdma.c | 67 ++++++++++++++-------- drivers/spi/spi-imx.c | 61 +++++++++++++++++--- include/linux/platform_data/dma-imx-sdma.h | 8 ++- 7 files changed, 108 insertions(+), 40 deletions(-)