From patchwork Fri Nov 6 12:35:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 11887089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93AC1C55178 for ; Fri, 6 Nov 2020 12:42:43 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2639420639 for ; Fri, 6 Nov 2020 12:42:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="aWgiBMQQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2639420639 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=UodbvFJoTmnN4EdxtEUvJykyKdPzkQkKjVoK0rppcRw=; b=aWgiBMQQAwSd9yPf8QRuFKLX7E CrctK62VMEXAM0p8/x+ZCDX0HkRfunv3ZXmYBY2Kj5p8DKRPA/HKEovuuA53bCQal7k2Ar3EEcazs PLjiC09xumcaWqUtMC/wknMcjWIQF/J81O8i7KDrBC1uHfxBAiPxRP6T0jVcCxAa7d9BFqnNIyW+O XrtCHQFtLoXNDMx+GhuPJJYM4IxOrQYg0Y6N7lyWITtK8TQlKDYZba6d7uZnYFd9RvLIuht8+K9XU OUQ/VO4xwVW9cm+cW0kodE0+hYiq8EEpkQYp1hCddCVMVAaMAcsCWfIYCMQr7hp/N0TH1KuP/3lTi 1OAVsyRQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kb139-0004Bw-FB; Fri, 06 Nov 2020 12:41:03 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kb12g-0003th-IF for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 12:40:37 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4CSKjC42FvzLvMW; Fri, 6 Nov 2020 20:39:59 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Fri, 6 Nov 2020 20:39:56 +0800 From: John Garry To: , , , , , , , , , , Subject: [PATCH RFC v5 00/13] perf pmu-events: Support event aliasing for system PMUs Date: Fri, 6 Nov 2020 20:35:40 +0800 Message-ID: <1604666153-4187-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_074036_000559_AE0A2D6A X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, John Garry , qiangqing.zhang@nxp.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, linux-imx@nxp.com, kjain@linux.ibm.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently event aliasing and metrics for only CPU and uncore PMUs is supported. In fact, only uncore PMUs aliasing is supported for when the uncore PMUs are fixed for a CPU, which may not always be the case for certain architectures. This series adds support for PMU event aliasing and metrics for system and other uncore PMUs which are not tied to a specific CPU. For this, we introduce system event tables in generated pmu-events.c, which contain a per-SoC table of events of all its system PMUs. Each per-PMU event is matched by a "COMPAT" property. When creating aliased and metrics PMUs, we treat core/uncore and system PMUs differently: - For CPU PMUs, we always match for the event mapfile based on the CPUID. This has not changed. - For an system PMUs, we iterate through all the events in all the system PMU tables. Matches are based on the "COMPAT" property matching the PMU sysfs identifier contents, in /sys/bus/event_source/devices//identifier Uncore PMUs, may be matched via CPUID or same as system PMU, depending on whether the uncore PMU is tied to a specific CPUID. Initial reference support is also added for ARM SMMUv3 PMCG (Performance Monitor Event Group) PMU for HiSilicon hip09 platform with only a single event so far - see driver in drivers/perf/arm_smmuv3_pmu.c reference. Here is a sample output with this series on Huawei D06CS board: root@ubuntu:/# ./perf list [...] smmu v3 pmcg: smmuv3_pmcg.config_cache_miss [Configuration cache miss caused by transaction or(ATS or non-ATS)translation request. Unit: smmuv3_pmcg] smmuv3_pmcg.config_struct_access [Configuration structure access. Unit: smmuv3_pmcg] smmuv3_pmcg.cycles [Clock cycles. Unit: smmuv3_pmcg] smmuv3_pmcg.l1_tlb [SMMUv3 PMCG L1 TABLE transation. Unit: smmuv3_pmcg] smmuv3_pmcg.pcie_ats_trans_passed [PCIe ATS Translated Transaction passed through SMMU. Unit: smmuv3_pmcg] smmuv3_pmcg.pcie_ats_trans_rq [PCIe ATS Translation Request received. Unit: smmuv3_pmcg] smmuv3_pmcg.tlb_miss [TLB miss caused by incoming transaction or (ATS or non-ATS) translation request. Unit: smmuv3_pmcg] smmuv3_pmcg.trans_table_walk_access [Translation table walk access. Unit: smmuv3_pmcg] smmuv3_pmcg.transaction [Transaction. Unit: smmuv3_pmcg] root@ubuntu:/# ./perf stat -v -e smmuv3_pmcg.l1_tlb sleep 1 Using CPUID 0x00000000480fd010 -> smmuv3_pmcg_200100020/event=0x8a/ -> smmuv3_pmcg_200140020/event=0x8a/ -> smmuv3_pmcg_100020/event=0x8a/ -> smmuv3_pmcg_140020/event=0x8a/ -> smmuv3_pmcg_200148020/event=0x8a/ -> smmuv3_pmcg_148020/event=0x8a/ smmuv3_pmcg.l1_tlb: 0 1001221690 1001221690 smmuv3_pmcg.l1_tlb: 0 1001220090 1001220090 smmuv3_pmcg.l1_tlb: 101 1001219660 1001219660 smmuv3_pmcg.l1_tlb: 0 1001219010 1001219010 smmuv3_pmcg.l1_tlb: 0 1001218360 1001218360 smmuv3_pmcg.l1_tlb: 134 1001217850 1001217850 Performance counter stats for 'system wide': 235 smmuv3_pmcg.l1_tlb 1.001263128 seconds time elapsed root@ubuntu:/# Support is also added for imx8mm DDR PMU and HiSilicon hip09 uncore events. Some events for hip09 may not be accurate at the moment. Series is here: https://github.com/hisilicon/kernel-dev/tree/private-topic-perf-5.10-sys-pmu-events-v5 Kernel part is here: https://lore.kernel.org/lkml/1602149181-237415-1-git-send-email-john.garry@huawei.com/T/#mc34f758ab72f3d4a90d854b9bda7e6bbb90835b2 Differences to v4: - Drop hack for fixing metrics containing aliases which match multiple PMUs, and add a proper fix attempt - Rebase to acme perf/core from 30 Oct - Fix up imx8 event names according to request from Joakim Differences to v3: - Rebase to v5.9-rc7 - Includes Ian's uncore metric expressions Fix and another fix - Add hip09 uncore events - Tidy jevents.c changes a bit Differences to v2: - fixups for imx8mm JSONs - fix for metrics being repeated per PMU - use sysfs__read_str() - fix typo in PMCG JSON - drop evsel fix, which someone else fixed Differences to v1: - Stop using SoC id and use a per-PMU identifier instead - Add metric group sys events support - This is a bit hacky - Add imx8mm DDR Perf support - Add fix for parse events sel - without it, I get this spewed for metric event: assertion failed at util/parse-events.c:1637 Joakim Zhang (1): perf vendor events: Add JSON metrics for imx8mm DDR Perf John Garry (12): perf jevents: Add support for an extra directory level perf jevents: Add support for system events tables perf pmu: Add pmu_id() perf pmu: Add pmu_add_sys_aliases() perf vendor events arm64: Add Architected events smmuv3-pmcg.json perf vendor events arm64: Add hip09 SMMUv3 PMCG events perf vendor events arm64: Add hip09 uncore events perf evlist: Change perf_evlist__splice_list_tail() ordering perf metricgroup: Fix metrics using aliases covering multiple PMUs perf metricgroup: Split up metricgroup__print() perf metricgroup: Support printing metric groups for system PMUs perf metricgroup: Support adding metrics for system PMUs .../arch/arm64/freescale/imx8mm/sys/ddrc.json | 39 +++ .../arm64/freescale/imx8mm/sys/metrics.json | 18 ++ .../hisilicon/hip09/sys/smmu-v3-pmcg.json | 42 +++ .../hisilicon/hip09/sys/uncore-ddrc.json | 58 ++++ .../arm64/hisilicon/hip09/sys/uncore-hha.json | 82 ++++++ .../arm64/hisilicon/hip09/sys/uncore-l3c.json | 106 ++++++++ .../pmu-events/arch/arm64/smmuv3-pmcg.json | 58 ++++ tools/perf/pmu-events/jevents.c | 88 ++++++- tools/perf/pmu-events/pmu-events.h | 6 + tools/perf/util/evlist.c | 19 +- tools/perf/util/metricgroup.c | 247 +++++++++++++----- tools/perf/util/pmu.c | 96 +++++++ tools/perf/util/pmu.h | 3 + 13 files changed, 794 insertions(+), 68 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json create mode 100644 tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json Acked-By: Kajol Jain