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dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR04MB5184.eurprd04.prod.outlook.com (2603:10a6:803:5d::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.25; Wed, 2 Dec 2020 05:41:23 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3611.025; Wed, 2 Dec 2020 05:41:23 +0000 From: Liu Ying To: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems Date: Wed, 2 Dec 2020 13:33:35 +0800 Message-Id: <1606887219-5854-1-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0091.apcprd03.prod.outlook.com (2603:1096:4:7c::19) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0091.apcprd03.prod.outlook.com (2603:1096:4:7c::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3632.8 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: sVldsF9zuQUWCvCy5zP3bIhvO+foYQLCVVAghQASttE0Ri8jWMq9XzKh0yUdqDgoDRuVITOzu6ALT8wNcmrBaNB78RwttAy9d2dQBoV4cxu6VcRd5pjO9jNadwYbhiKx8Fu77riOkg64LcMcXqDNH5BAnMPhmLE8NR0Mdju5ON599XXvLTMiMFLkTnIwhvN0Pr8LpIpn/sbljd4U5xmK4wue/Jfsv+FDIj1YDKIewbThphIVYfuk9WUqsM7ZeG9l+QNTScfMBzcA76TQ2hxmm213m9SuTuLD9jq57zqC/yqEcNyC7j5IcjqfThUqs9Bqr7wf7q1/6f2BaUhSvOAH6m4zapx67HUF1VmBb3hDtVwwnRurxgmlhI8Qsx5KD48RyXIgT1RgJJxkn2Tg8gw2YTZfUpmlxX6dKINjZ7qITT9fhhhlbS3GN5dD89svLT53EqGm7nqixVQ5IaB/1CeZRhxqY4Gm9HW3DTjR7bBzgAG4VJmLPr1ZKl/F00Y3PVtEnXd71sACTgrp7wW86fie1ixFM+Wz9l1lHmHHUVZJBC1j6Mxfnw2H7UGwMtBBMDhYF0D+/Vm8SB8wypId6GoXnq914olrkLx9JiTG6hYWc7KuM0V7FNgDHl6a6UtlA39m2v+YmTNNyFONYrxOd+O6R69y2Vt8dV7AWzLOx74Rk4KLJOjY4GJCvXFdj9axOcVm7usPGUVZLPF40OitARjZuz0+euoVsZtchEX24myf8YPq9J6xTc3WGmP+Ll9N8zfS4UQr5jxw2XhRmNyV4xFI5W2mJ3+wO9bgDWc4yi2obGcLx9i+qBLmbGqu3tAWd/42C2ixgxrBX9DYt53GVsSzasx0N0b40yrFDCtfiFJTkTu8Sy9/gEJhwKc+ZW2j/P7eV6K3xQ0znLsj12kz4vBeM9OCKAVUa/9Wd/fEUXPRRGhVFmduzwBvDSbClKYOQePeujjFqBnOlKdTWzvNPhckhylJB63yt9W5UXqXvSkMWoo+5IM1JlHSUJbYmcNY08gH X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: cfc1e6df-7019-447b-2e2e-08d89684e6bc X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2020 05:41:22.8344 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /sKtHzoz5g2JNfR1xdPFLmBVa0BqBxWg+6yEsKCZnYUxJQOvK3Esxk3VZwDcG13oggM7jc1P1BEnZJPXS5WUlA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5184 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201202_004131_511929_D24221EF X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aisheng.dong@nxp.com, sboyd@kernel.org, shawnguo@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, s.hauer@pengutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems. With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got by drivers. v1->v2: * Drop LPCG clocks as they can be registered directly in an in-tree new DT binding way. * Add DC0 bypass clocks support. * Correct the way to register DC0 display clocks. * Trivial tweak. Liu Ying (4): clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems drivers/clk/imx/clk-imx8qxp.c | 26 ++++++++++++++++++++++++-- include/dt-bindings/clock/imx8-clock.h | 2 ++ 2 files changed, 26 insertions(+), 2 deletions(-)