From patchwork Fri Dec 4 11:10:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 11951505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17194C4361A for ; Fri, 4 Dec 2020 11:17:02 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B24EB22525 for ; Fri, 4 Dec 2020 11:17:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B24EB22525 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=jGSCtGxphkPn24H18ABTT6WnPNA1dm/1d659cnxoRDw=; b=Vvvg7UZ/5vCPXJr7Joot5yVdYB MunfHvJb0XbHKP+ChL8yavIjfFMoy1UkCWEKUsNs2aigEze9B9nt3s9xdrblQLN9zdP+jCEApCt/W jTtcX1/bxH0P4XvaOfAcApl5XL80oQzTLsDZEyy57Ta7Axu+VyJkmCzgMN9PsQoKDTew/QR/v1xZb 8VvJyBKAWEUbhLK9Gc6X29z2WrJEZW3YOO+sINfFwDOm4j308iBy/sbHSWhaddQczDjDSUz62xQMQ 7bwU8swegvy/HoRbIhTcJpY+6RQ4NwaayzsOCf3Fq3Crf+n1XEAOessZcpBAFS5voFTsL9KpPsktt d2Lcz4UA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kl93l-0003l6-NB; Fri, 04 Dec 2020 11:15:33 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kl93K-0003Z9-LW for linux-arm-kernel@lists.infradead.org; Fri, 04 Dec 2020 11:15:09 +0000 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CnVTh0n2sz15XXd; Fri, 4 Dec 2020 19:14:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Fri, 4 Dec 2020 19:14:23 +0800 From: John Garry To: , , , , , , , , , , Subject: [PATCH v6 00/10] perf pmu-events: Support event aliasing for system PMUs Date: Fri, 4 Dec 2020 19:10:06 +0800 Message-ID: <1607080216-36968-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201204_061507_240646_7B101C54 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ak@linux.intel.com, linux-kernel@vger.kernel.org, kjain@linux.ibm.com, John Garry , linuxarm@huawei.com, qiangqing.zhang@nxp.com, zhangshaokun@hisilicon.com, kim.phillips@amd.com, linux-arm-kernel@lists.infradead.org, kan.liang@linux.intel.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently event aliasing and metrics is supported for only CPU and uncore PMUs. More specifically, only uncore PMUs aliasing is supported for when the uncore PMUs are fixed for a CPU, which may not always be the case for certain architectures. This series adds support for PMU event aliasing and metrics for system and other uncore PMUs which are not tied to a specific CPU. For this, we introduce system event tables in generated pmu-events.c, which contain a per-SoC table of events of all its system PMUs. Each per-PMU event is matched by a "COMPAT" property. When creating aliases and metrics for PMUs, we treat core/uncore and system PMUs differently: - For CPU PMUs, we always match for the event mapfile based on the CPUID. This has not changed. - For an system PMUs, we iterate through all the events in all the system PMU tables. Matches are based on the "COMPAT" property matching the PMU sysfs identifier contents, in /sys/bus/event_source/devices//identifier Uncore PMUs, may be matched via CPUID or same as system PMU, depending on whether the uncore PMU is tied to a specific CPUID. Initial reference support is also added for for imx8mm DDR PMU, and it looks like this for the user: $ ./perf list metric List of pre-defined events (to be used in -e): Metric Groups: No_group: imx8mm_ddr_read.all [bytes all masters read from ddr based on read-cycles event. Unit: imx8_ddr ] imx8mm_ddr_write.all [bytes all masters write to ddr based on write-cycles event. Unit: imx8_ddr ] $ sudo ./perf stat -v -M imx8mm_ddr_read.all sleep 1 metric expr imx8mm_ddr.read_cycles * 4 * 4 for imx8mm_ddr_read.all found event imx8mm_ddr.read_cycles adding {imx8mm_ddr.read_cycles}:W imx8mm_ddr.read_cycles -> imx8_ddr0/event=0x2a/ imx8mm_ddr.read_cycles -> imx8_ddr1/event=0x2a/ Control descriptor is not initialized imx8mm_ddr.read_cycles: 2 1001455480 1001455480 imx8mm_ddr.read_cycles: 3 1001454940 1001454940 Performance counter stats for 'system wide': 5 imx8mm_ddr.read_cycles # 0.1 KB imx8mm_ddr_read.all 1.001493170 seconds time elapsed I have not included HiSilicon hip09 events from earlier RFC since it is a new platform and not all event codes are available yet, so they can come later. Series is here: https://github.com/hisilicon/kernel-dev/tree/private-topic-perf-5.10-sys-pmu-events-v6 Kernel part accepted / pending in the following: - https://lore.kernel.org/linux-arm-kernel/160631703729.2332128.13220150013299384201.b4-ty@kernel.org/ - https://lore.kernel.org/linux-devicetree/9468d155-f285-0d03-181b-fe378042f858@huawei.com/ Differences to v5: - Add tags from Kajol Jain (thanks) - For now, don't include HiSilicon hip09 events until all event codes available - Rebase Differences to v4: - Drop hack for fixing metrics containing aliases which match multiple PMUs, and add a proper fix attempt - Rebase to acme perf/core from 30 Oct - Fix up imx8 event names according to request from Joakim Joakim Zhang (1): perf vendor events: Add JSON metrics for imx8mm DDR Perf John Garry (9): perf jevents: Add support for an extra directory level perf jevents: Add support for system events tables perf pmu: Add pmu_id() perf pmu: Add pmu_add_sys_aliases() perf evlist: Change perf_evlist__splice_list_tail() ordering perf metricgroup: Fix metrics using aliases covering multiple PMUs perf metricgroup: Split up metricgroup__print() perf metricgroup: Support printing metric groups for system PMUs perf metricgroup: Support adding metrics for system PMUs .../arch/arm64/freescale/imx8mm/sys/ddrc.json | 39 +++ .../arm64/freescale/imx8mm/sys/metrics.json | 18 ++ tools/perf/pmu-events/jevents.c | 87 +++++- tools/perf/pmu-events/pmu-events.h | 6 + tools/perf/util/evlist.c | 19 +- tools/perf/util/metricgroup.c | 254 +++++++++++++----- tools/perf/util/pmu.c | 96 +++++++ tools/perf/util/pmu.h | 3 + 8 files changed, 451 insertions(+), 71 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx8mm/sys/metrics.json