From patchwork Wed Feb 3 07:51:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 12063653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E49FBC433E6 for ; Wed, 3 Feb 2021 07:53:42 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 857F564E43 for ; Wed, 3 Feb 2021 07:53:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 857F564E43 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=dO+JVzYbp11mE5EJQn+x0OzM03FZPwtOZx+jL99DOs0=; b=FnWFmIr1a7hTblH13mvu3KZxfQ CcHemw0XP7x8ZnSoytOd0BkVnyzElVh29CF0u9yrhiakwcHbI/WkbpWZrCp+NKGrBcWo5azLrQZ79 KM+JUjqEGW7R1C4RdjizV0tlZbW0S9zOqPFPFcUPQQqLICei4hxJY4s64nFZpnmDFOnTdqoD7keb7 BYjnTAPb8CKccRPNlaP55PkFX85KWS88+T0FaBqUE0k8kIUcydbRs08v9GyNyzpqgdoiHzl0+4oxj EPPLHYzQuOnwoNKpk3yfMEJKmFQ7PVlnMmS48uW5SrxpKjccf0ikRlCTm0IvJT0C2h66x9Wd27DRh +oxRqBlg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7Cxm-0000NJ-JL; Wed, 03 Feb 2021 07:52:34 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7CxT-0000BK-B0 for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2021 07:52:18 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DVv430C7KzMVDf; Wed, 3 Feb 2021 15:50:27 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Wed, 3 Feb 2021 15:51:57 +0800 From: Shaokun Zhang To: Subject: [PATCH v2 0/8] Add support for HiSilicon Hip09 uncore PMU driver Date: Wed, 3 Feb 2021 15:51:00 +0800 Message-ID: <1612338668-40493-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_025217_391686_3989B9A1 X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Qi Liu , John Garry , Shaokun Zhang , Jonathan Cameron , Will Deacon Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patchset adds support for HiSilicon Hip09 SoC uncore PMUs driver which is PMU v2 and it includes: (a) Refactor interrupt registration and handler function for later new uncore PMU driver in patch1; (b) Update the PMU version suffiex for existing driver in patch2 (b) Some new functions are added on L3C/HHA PMU in patch3/4; (c) New DDRC PMU model is supported using programable counter and supports more events in patch5; (d) Add new modules SLLC and PA PMU drivers in patch6/7; (e) Update the perf document for the new functions and modules in patch8; ChangeLog v1-->v2: 1. Address John's comments and fix some typos 2. Add John's Reviewed-by tags Cc: Mark Rutland Cc: Will Deacon Cc: John Garry Cc: Jonathan Cameron Cc: Qi Liu Shaokun Zhang (8): drivers/perf: hisi: Refactor code for more uncore PMUs drivers/perf: hisi: Add PMU version for uncore PMU drivers. drivers/perf: hisi: Add new functions for L3C PMU drivers/perf: hisi: Add new functions for HHA PMU drivers/perf: hisi: Update DDRC PMU for programable counter drivers/perf: hisi: Add support for HiSilicon SLLC PMU driver drivers/perf: hisi: Add support for HiSilicon PA PMU driver docs: perf: Add new description on HiSilicon uncore PMU v2 Documentation/admin-guide/perf/hisi-pmu.rst | 54 +++ drivers/perf/hisilicon/Makefile | 3 +- drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 348 +++++++++++------ drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 301 ++++++++++----- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 353 ++++++++++++----- drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 500 ++++++++++++++++++++++++ drivers/perf/hisilicon/hisi_uncore_pmu.c | 76 +++- drivers/perf/hisilicon/hisi_uncore_pmu.h | 19 +- drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 531 ++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 2 + 10 files changed, 1882 insertions(+), 305 deletions(-) create mode 100644 drivers/perf/hisilicon/hisi_uncore_pa_pmu.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c