From patchwork Mon Nov 5 14:36:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 10668371 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69C6F15A6 for ; Mon, 5 Nov 2018 14:37:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 586CF29906 for ; Mon, 5 Nov 2018 14:37:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4C7EC2990E; Mon, 5 Nov 2018 14:37:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DCEE329906 for ; Mon, 5 Nov 2018 14:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=30lpBoMZkbEc6sO95Mo8LTyYxNcenTCwlBJeoOB9NU4=; b=XJw2ipY+1/2V4m Vw70drpmgYAVKXs2IweqQCJVpB854w4ENJGxONNrEK1EsaOGXR/FKQuOCZhJHNygGlb7o4mS+XXcg bcsPhxsTSvsdc9D2cR+7urvkumpfqxKgYfg8TeV8CY/tSWo9zeN87tRKANemTpAadkva5w5pGAIIg BTGtA63Og1MZR5kmbqhrk8HJlVbKz33TsrB78MEiq2bfRIPcwZy3j+8Lef5NkDwblWWElJOQGrPbi 3QtrlV/dkEHwgSLgSnNqT8MvUsOYmM0wjxoUttan00qnq2c3C8fThp+k53K8PFvKfbaizq+ugf6p9 TZv/mx0s7gr3V8ZzUVDw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gJg0Q-0001tK-2f; Mon, 05 Nov 2018 14:37:30 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gJfzw-0001Ax-EI for linux-arm-kernel@lists.infradead.org; Mon, 05 Nov 2018 14:37:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4924A78; Mon, 5 Nov 2018 06:36:48 -0800 (PST) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.196.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B1F23F944; Mon, 5 Nov 2018 06:36:47 -0800 (PST) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH 0/4] Workaround for Cortex-A76 erratum 1165522 Date: Mon, 5 Nov 2018 14:36:12 +0000 Message-Id: <20181105143617.120602-1-marc.zyngier@arm.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181105_063700_538156_DB47DAF9 X-CRM114-Status: GOOD ( 11.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Will Deacon , Christoffer Dall , Suzuki K Poulose Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Early Cortex-A76 suffer from an erratum that can result in invalid TLBs when the CPU speculatively executes an AT instruction in the middle of a guest world switch, while the guest virtual memory configuration is in an inconsistent state. We handle this issue by mandating the use of VHE and making sure that the guest context is fully installed before switching HCR_EL2.TGE to zero. This ensures that a speculated AT instruction is either executed on the host context (TGE set) or the guest context (TGE clear), and that there is no intermediate state. Marc Zyngier (4): KVM: arm64: Rework detection of SVE, !VHE systems KVM: arm64: Allow implementations to be confined to using VHE arm64: KVM: Install stage-2 translation before enabling traps on VHE arm64: KVM: Implement workaround for Cortex-A76 erratum 1165522 Documentation/arm64/silicon-errata.txt | 1 + arch/arm/include/asm/kvm_host.h | 3 ++- arch/arm64/Kconfig | 12 ++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/kvm_host.h | 14 ++++++++++---- arch/arm64/include/asm/kvm_hyp.h | 6 ++++++ arch/arm64/kernel/cpu_errata.c | 8 ++++++++ arch/arm64/kvm/hyp/switch.c | 16 +++++++++++++++- virt/kvm/arm/arm.c | 17 ++++++++++++----- 9 files changed, 68 insertions(+), 12 deletions(-)