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Thu, 31 Jan 2019 01:24:16 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH V4 0/7] Add CPUidle support for Tegra210 Date: Thu, 31 Jan 2019 17:24:03 +0800 Message-ID: <20190131092410.28222-1-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548926658; bh=ENHYVgcqOP6xBR3gwZRGINRwAQgtBFPqvTozpD28GI0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=UWDR0ZHWDVrmOB29Q3eKa4JCgvg3cMPVudpjVQBwfNWBl1+muV0kBfpnG/MomjvOm GQJ0oK1I9QLon1rZdv7CuhWg8GhOumDogzJi06QBhlxcMEJwTejR5fu5ZYhriMwGWK /XF8RVsDXSuL4ujbtG6ETOCpFCDS4FtUYTXGUvbhCVkrA5+sPVmhFjdrgAcF5ydek+ FLEsrehk9dwVtwMflm9u9mI6aC4oSwHUw4OnBG6o8ybYOxzTOgcXz/JNZNXP3Du78j DqqIaH67QbgmiuK2nZMCvzmnePZHd8jT0K2Krzx+JPUtBPeeCbgws3KGGbGtaWY04J V6/ETX0jrS4tA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190131_012416_894737_EAC1B913 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch series adds CPUidle support for Tegra210, which supports power-down state (C7) for CPU cores. And due to arch timer cannot work across CPU core power-down and power on reset signal event. We introduce Tegra210 timer driver to work as clock event device. So it can be the wake-up source of CPU cores when they idled in the power-down state. Fixed in V4: * merge timer-tegra210.c into timer-tegra20.c * add a new patch to select TEGRA_TIMER by default for Tegra210 Fixed in V3: * use timer-of API for Tegra210 timer driver Fixed in V2: * list all the timer IRQs in the binding doc and dts file * add error clean-up code in timer driver * add entry-latency-us and exit-latency-us properties for idle-states DT node Joseph Lo (7): dt-bindings: timer: add Tegra210 timer clocksource: tegra: add Tegra210 timer support soc/tegra: default select TEGRA_TIMER for Tegra210 arm64: dts: tegra210: fix timer node arm64: dts: tegra210: add CPU idle states properties arm64: dts: tegra210-p2180: Enable CPU idle support arm64: dts: tegra210-smaug: Enable CPU idle support .../bindings/timer/nvidia,tegra210-timer.txt | 36 ++ .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 + arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 +- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-tegra20.c | 369 +++++++++++++----- drivers/soc/tegra/Kconfig | 1 + include/linux/cpuhotplug.h | 1 + 8 files changed, 352 insertions(+), 103 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt