From patchwork Mon Mar 25 18:30:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 10869813 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4DE1F139A for ; Mon, 25 Mar 2019 18:30:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3673728CE3 for ; Mon, 25 Mar 2019 18:30:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2ACC3291EE; Mon, 25 Mar 2019 18:30:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BB34528CE3 for ; Mon, 25 Mar 2019 18:30:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=qk0egoJs3JLJNJH/ZER5WxD8owPFu06XXGBHKn7U6eA=; b=u2SfZAev33j9Zy EXX2ayVePvI4yx5P+xDdG9CNp8ZWUfLS5sjekGRrdTSpuSZ24XNRYULyIf94FZb6SPAH2i1fKit3k rig5D4T6Igt7fRZ631USdZogqhhwhSw1VYYscsvn5Y/4FFn9dZa61gZcXAv8PBjphEn6KwFn5sNtA SsW8jK77g7H+jsL8cdF5N7i+otyoYyZCbAfTezwRmiWxlyH07Cs7XX4YQh1A/XdbW6KmIBNO4EPWY Pe3cDNVFMqfa8p/TeisZ3ybGUQn68kLtr5Zt7WZ/WJT09ZfThcJS4LSjeuxgd3FPNe/9IJsCb/m7M DRpqOx0uVmbbRPJf306g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h8UMm-0004LY-8Z; Mon, 25 Mar 2019 18:30:36 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h8UMS-0004Bu-LY for linux-arm-kernel@lists.infradead.org; Mon, 25 Mar 2019 18:30:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52E431596; Mon, 25 Mar 2019 11:30:13 -0700 (PDT) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E0EB13F575; Mon, 25 Mar 2019 11:30:11 -0700 (PDT) From: Andrew Murray To: Christoffer Dall , Marc Zyngier Subject: [PATCH v4 0/6] KVM: arm/arm64: add support for chained counters Date: Mon, 25 Mar 2019 18:30:00 +0000 Message-Id: <20190325183006.33115-1-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190325_113016_723171_18BDB7A9 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Thierry , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Suzuki K Poulose Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP ARMv8 provides support for chained PMU counters, where an event type of 0x001E is set for odd-numbered counters, the event counter will increment by one for each overflow of the preceding even-numbered counter. Let's emulate this in KVM by creating a 64 bit perf counter when a user chains two emulated counters together. Testing has been performed by hard-coding hwc->sample_period in __hw_perf_event_init (arm_pmu.c) to a small value, this results in regular overflows (for non sampling events). The following command was then used to measure chained and non-chained instruction cycles: perf stat -e armv8_pmuv3/long=1,inst_retired/u \ -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ count=10 | gzip > /dev/null The reported values were identical (and for non-chained was in the same ballpark when running on a kernel without this patchset). Debug was added to verify that the guest received overflow interrupts for the chain counter. For chained events we only support generating an overflow interrupt on the high counter. We use the attributes of the low counter to determine the attributes of the perf event. Changes since v3: - Simplify approach by not creating events lazily and by introducing a struct kvm_pmc_pair to represent the relationship between adjacent counters. - Rebase onto v5.1-rc2 Changes since v2: - Rebased onto v5.0-rc7 - Add check for cycle counter in correct patch - Minor style, naming and comment changes - Extract armv8pmu_evtype_is_chain from arch/arm64/kernel/perf_event.c into a common header that KVM can use Changes since v1: - Rename kvm_pmu_{enable,disable}_counter to reflect that they can operate on multiple counters at once and use these functions where possible - Fix bugs with overflow handing, kvm_pmu_get_counter_value did not take into consideration the perf counter value overflowing the low counter - Ensure PMCCFILTR_EL0 is used when operating on the cycle counter - Rename kvm_pmu_reenable_enabled_{pair, single} and similar - Always create perf event disabled to simplify logic elsewhere - Move PMCNTENSET_EL0 test to kvm_pmu_enable_counter_mask Andrew Murray (6): KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions KVM: arm/arm64: extract duplicated code to own function KVM: arm/arm64: re-create event when setting counter value arm64: perf: extract chain helper into header KVM: arm/arm64: represent paired counters with kvm_pmc_pair KVM: arm/arm64: support chained PMU counters arch/arm64/include/asm/perf_event.h | 5 + arch/arm64/kernel/perf_event.c | 2 +- arch/arm64/kvm/sys_regs.c | 4 +- include/kvm/arm_pmu.h | 23 +- virt/kvm/arm/pmu.c | 396 +++++++++++++++++++++++----- 5 files changed, 359 insertions(+), 71 deletions(-)